Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory.

Abstract: Embodiments of the invention include a method performed in a media access control (MAC) forwarding control module within a network element for looking up a MAC address and interface (I/F) identifier pair (MAC-I/F pair) from a MAC forwarding data structure that comprises a first tier data structure and a plurality of second tier data structures. The MAC forwarding data structure utilizes compressed keys to index each of the plurality second tier data structures. The compressed key is generated with a desired MAC address and a mask bit list that corresponds with enough bit positions such that all MAC addresses in second tier data structure can be uniquely addressed with just the values of each MAC address in the bit positions listed. As such, the MAC forwarding data structure is constructed so that the total cost of a lookup with the compressed key technique is deterministic and, therefore, O(1).

Abstract: Embodiments of the invention include a method performed by a bank aware mtrie control module for distributing a plurality of mtrie levels across a plurality of memory banks. The bank aware mtrie control module identifies the plurality of memory banks present and identifies one or more mtrie blocks in one or more mtrie levels, each mtrie block is an array of mtrie nodes associated with an mtrie level. The bank aware mtrie control module stores each mtrie block in one of the plurality of memory banks, all mtrie nodes in a given mtrie block are stored in the same memory bank. For each subsequent mtrie level, the bank aware mtrie control module ensures that each of the mtrie blocks in that mtrie level is stored in one of the plurality of memory banks other than the memory bank storing mtrie blocks of an immediately previous mtrie level.

Abstract: Embodiments of the invention include a method for avoiding memory bandwidth utilization during packet processing. The packet processing core receives a plurality of packets. The packet processing core identifies the packet's quality of service (QoS) descriptor. The packet processing core determines that at least one packet should be moved to an off-chip packet stored prior to the packet being transmitted to the egress port. The packet processing core bases that determination, at least in part, on the packet's QoS descriptor. The packet processing core moves the determined packets to the off-chip packet store. The packet processing core determines that at least one packet should not be moved to the off-chip packet store prior to the packet being transmitted to the egress port. This determination is also made, at least in part, based on the packet's QoS descriptor.

Abstract: Embodiments of the invention include a method performed in a packet processor core for policing a packet through a hierarchical policer coupled to one or more policing requestors. The hierarchical policer has a plurality of meter levels including an initial level and one or more subsequent levels. The hierarchical policer creates a meter result at the meter of each meter level using packet characteristics and a meter state for that meter level. The hierarchical policer generates meter level outputs that classify the packet for each meter level and for at least one of the subsequent levels the meter level output is based on the meter level output from a previous meter level. The hierarchical policer performs a meter combine operation that produces a final packet output attribute from the combination of the meter level outputs. The hierarchical policer returns the final packet output attribute to a policing requestor.

Abstract: Embodiments of the invention a method for policing a packet at line rate. A hierarchical policer receives a policer request comprising packet characteristics and identifying request configuration information. The hierarchical policer retrieves meter states specified by the request configuration information. The hierarchical policer processes packet characteristics through meters to generate a meter result. The hierarchical policer generates a hierarchical policer table lookup address using a plurality of meter types, a plurality of input color controls, one or more of the packet characteristics, the meter results, and a plurality of coupling algorithm identifiers. The hierarchical policer reads a hierarchical meter result from a hierarchical policer result table, containing at least a final output packet attribute that classifies the packet. The hierarchical policer updates one or more of the meter states based on the plurality of meter state results.

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory.

Abstract: Embodiments of the invention include a method performed in a media access control (MAC) forwarding control module within a network element for looking up a MAC address and interface (I/F) identifier pair (MAC-I/F pair) from a MAC forwarding data structure that comprises a first tier data structure and a plurality of second tier data structures. The MAC forwarding data structure utilizes compressed keys to index each of the plurality second tier data structures. The compressed key is generated with a desired MAC address and a mask bit list that corresponds with enough bit positions such that all MAC addresses in second tier data structure can be uniquely addressed with just the values of each MAC address in the bit positions listed. As such, the MAC forwarding data structure is constructed so that the total cost of a lookup with the compressed key technique is deterministic and, therefore, O(1).

Abstract: A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.

Abstract: A scheduler utilizes a data structure in the form of an augmented, pruned, radix tree to implement 2-key scheduling.

Abstract: A scheduler utilizes a data structure in the form of an augmented, pruned, radix tree to implement 2-key scheduling.