Abstract: A method for estimating accuracy of an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor and the accuracy of the on-chip temperature sensor is estimated from the simulation. A computer system for estimating accuracy of an on-chip temperature sensor is also provided. A computer-readable medium having instructions adapted to input a representative power supply waveform having noise into a simulation of an on-chip temperature sensor and estimate accuracy of the on-chip temperature sensor from the simulation is provided.

Abstract: An apparatus that uses a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method for using a linear voltage regulator to reject power supply noise in a temperature sensor is provided. Further, a method and apparatus that uses a differential amplifier with a source-follower output stage as a linear voltage regulator for a temperature sensor is provided.

Abstract: A method and apparatus that uses the difference between two nodal voltages, such as a temperature-independent voltage and a temperature-dependent voltage, to determine the actual temperature at a point on an integrated circuit is provided. Further, a method and apparatus that converts a difference between nodal voltages in an integrated circuit from an analog to a digital quantity on the integrated circuit such that the difference in voltage may be used by an on-chip digital system is provided. Further, a method and apparatus for quantifying a difference in voltage between a first node and a second node of a temperature sensor is provided.

Abstract: An integrated circuit that uses electrical fuses to store calibration information of a thermal monitoring device residing on the integrated circuit is provided. Such an integrated circuit allows a service processor of a computer system to query the integrated circuit for calibration information so that an accurate actual temperature measurement may be determined. Further, a method for reading and storing temperature calibration information on-chip is provided.

Abstract: A method for using a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. Further, an apparatus that uses a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. The apparatus generates a temperature-dependent voltage and a temperature-independent voltage using an amplifier stage that generates a feedback signal; a startup stage that generates a startup signal dependent on the feedback signal; and an output stage that outputs the temperature-dependent voltage and the temperature-independent voltage dependent on the feedback and startup signals.

Abstract: A method for optimizing loop bandwidth in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and the loop bandwidth of the delay looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a delay locked loop is provided.

Abstract: A method for estimating jitter in a delay locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a delay locked loop is provided.

Abstract: A method for optimizing a decoupling capacitance for an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor; a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor is determined; and an amount of the decoupling capacitance is adjusted until the difference falls below a pre-selected value. A computer system for optimizing a decoupling capacitance for an on-chip temperature sensor is also provided. A computer-readable medium having recorded thereon instructions executable by a processor for optimizing a decoupling capacitance for an on-chip temperature sensor is further provided.

Abstract: A method for optimizing decoupling capacitance in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and an amount of the decoupling capacitance is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing decoupling capacitance in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize decoupling capacitance in a phase locked loop is provided.

Abstract: A method for optimizing decoupling capacitance in a delay locked loop is provided. A representative power supply waveform having noise is input into a simulation of the delay locked loop; an estimate of jitter is determined; and an amount of the decoupling capacitance is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing decoupling capacitance in a delay locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize decoupling capacitance in a delay locked loop is provided.

Abstract: A method for optimizing loop bandwidth in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and the loop bandwidth of the phase looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a phase locked loop is provided.

Abstract: A method for estimating jitter in a phase locked loop is provided. The estimation is determined from a simulation that uses a representative power supply waveform having noise as an input. Further, a computer system for estimating jitter in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to estimate jitter in a phase locked loop is provided.

Abstract: A method for using a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. Further, an apparatus that uses a low voltage power supply to generate a temperature-independent voltage and temperature-dependent voltage is provided. The apparatus generates a temperature-dependent voltage and a temperature-independent voltage using an amplifier stage that generates a feedback signal; a startup stage that generates a startup signal dependent on the feedback signal; and an output stage that outputs the temperature-dependent voltage and the temperature-independent voltage dependent on the feedback and startup signals.

Abstract: A technique Readjusting a bias-generator in a delay locked loop after fabrication of the delay locked loop. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated.

Abstract: A delay locked loop that uses a differential push/pull buffer is provided. The differential push/pull buffer of the DLL is used to create a buffered output that closely follows the characteristics of the buffer's input over a range of temperature, power supply noise operating conditions, and process (manufacturing) variations. Further, an integrated circuit that contains a delay locked loop that uses a differential push/pull buffer is provided. Further, a delay locked loop with means for buffering a delayed signal is provided. Further, a method for buffering a delayed clock signal using a differential push/pull buffer is provided.

Abstract: A technique for adjusting a bias-generator in a phase locked loop after fabrication of the phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated.

Abstract: An integrated on-chip process, temperature, and voltage sensor is provided. Further, a method to monitor a process corner, temperature, and voltage on a computer chip is provided. Further, an on-chip voltage monitor is provided. Further, a method to monitor a voltage on a section of a computer chip is provided. Further, an integrated testing module having voltage, temperature, and sensor components is provided.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A method for reducing voltage variation in a PECL based component has been developed. The method includes powering up a PECL based component, such as a receiver circuit for a PLL, and activating or inserting a shunting resistance across the power supply terminals of a PECL power supply. The shunting resistance is inserted in parallel with the PECL based component, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A method for reducing voltage variation in the power supply system of a phase locked loop has been developed. The method includes powering up a phase locked loop and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the phase locked loop, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.