Patents by Inventor Brian Brunn
Brian Brunn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11262786Abstract: A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.Type: GrantFiled: December 16, 2020Date of Patent: March 1, 2022Assignee: Silicon Laboratories Inc.Inventors: Hegong Wei, Brian Brunn, Paul Zavalney
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Patent number: 9258018Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.Type: GrantFiled: October 20, 2014Date of Patent: February 9, 2016Assignee: MARVELL WORLD TRADE LTD.Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
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Patent number: 9166632Abstract: A receiver including a mixer, a clock generator, a plurality of capacitances, a plurality of resistances, and a controller. The mixer includes a plurality of switches. The clock generator is configured to generate clock signals to drive the plurality of switches of the mixer. The plurality of capacitances couples the clock signals to respective inputs of the plurality of switches. The plurality of resistances couples to the respective inputs of the plurality of switches. The controller is configured to output a first signal to the plurality of resistances. The first signal determines one or more attributes of the clock signals. One or more switching characteristics of the plurality of switches of the mixer are based on the one or more attributes of the clock signals.Type: GrantFiled: June 10, 2014Date of Patent: October 20, 2015Assignee: Marvell International LTD.Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
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Patent number: 9000815Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.Type: GrantFiled: March 15, 2013Date of Patent: April 7, 2015Assignee: Marvell World Trade Ltd.Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
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Publication number: 20150038095Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.Type: ApplicationFiled: October 20, 2014Publication date: February 5, 2015Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
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Patent number: 8942312Abstract: This disclosure describes techniques for modulating data. In one embodiment, these techniques include receiving an I or Q value, generating a time-shifted sample of a shaped pulse based on the I or Q value, and providing the time-shifted sample to a digital-to-analog converter.Type: GrantFiled: August 12, 2013Date of Patent: January 27, 2015Assignee: Marvell International Ltd.Inventors: Brian Brunn, Marc Leroux, Gregory Uehara
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Patent number: 8868015Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.Type: GrantFiled: May 19, 2010Date of Patent: October 21, 2014Assignee: Marvell World Trade Ltd.Inventors: Gregory Uehara, Chao Yang, Ruoxin Jiang, Fernando De Bernardinis, Alessandro Venca, Rinaldo Castello, Marc Leroux, Brian Brunn
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Patent number: 8831143Abstract: A method for DC offset cancellation includes defining, in a range of possible gain values for operating a direct conversion receiver, multiple sub-ranges of the possible gain values. Multiple DC offset correction values for the respective sub-ranges are stored in a memory. Upon detecting at the receiver that a gain of the receiver has changed from a first sub-range to a second sub-range, DC offset cancellation is initiated based on a DC offset correction value stored for the second sub-range and on a condition relating to past operation in the second sub-range.Type: GrantFiled: December 22, 2013Date of Patent: September 9, 2014Assignee: Marvell World Trade Ltd.Inventors: Rony Ashkenazi, Alexander Zaslavsky, Gregory Uehara, Brian Brunn
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Patent number: 8787511Abstract: A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.Type: GrantFiled: October 22, 2013Date of Patent: July 22, 2014Assignee: Marvell World Trade Ltd.Inventors: Brian Brunn, Gregory Uehara, Sehat Sutardja
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Patent number: 8750437Abstract: A receiver including a mixer configured to generate (i) a first output and (ii) a second output, a first capacitance coupled to the first output, and a second capacitance coupled to the second output, A controller is configured to program (i) the first capacitance and (ii) the second capacitance to a first capacitance value in response to operating the receiver in a first mode, and program (i) the first capacitance and (ii) the second capacitance to a second capacitance value in response to operating the receiver in a second mode. The first capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the first mode. The second capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the second mode.Type: GrantFiled: March 25, 2013Date of Patent: June 10, 2014Assignee: Marvell International Ltd.Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
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Publication number: 20140105331Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.Type: ApplicationFiled: December 22, 2013Publication date: April 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Rony Ashkenazi, Alexander Zaslavsky, Gregory Uehara, Brian Brunn
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Patent number: 8681893Abstract: This disclosure describes techniques for using a pulse look-up-table to replace FIR filters used to implement modulation schemes, such as the modulation schemes used by various wireless communication technologies. In some embodiments the pulse look-up-table is segmented and minimized so that the pulse look-up-table can be used with complex modulation schemes.Type: GrantFiled: October 7, 2009Date of Patent: March 25, 2014Assignee: Marvell International Ltd.Inventors: Brian Brunn, Marc Leroux
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Publication number: 20140044224Abstract: A system including a filter and a downconverter. The filter is configured to receive, from a node, (i) a first signal and (ii) a second signal, and filter the second signal. The filter includes a first input impedance. The filter comprises a first plurality of switches and a first circuit. The first plurality of switches is configured to communicate with the node. The first plurality of switches is clocked at a first frequency. The first frequency is based on a frequency of the first signal. The first circuit is configured to communicate with an output of the plurality of switches. The first circuit includes a second input impedance. The second input impedance is different than the first input impedance. The downconverter is configured to (i) receive the first signal and (ii) downconvert the first signal. The filter and the downconverter are connected in parallel to the node.Type: ApplicationFiled: October 22, 2013Publication date: February 13, 2014Applicant: Marvell World Trade Ltd.Inventors: Brian Brunn, Gregory Uehara, Sehat Sutardja
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Patent number: 8638883Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.Type: GrantFiled: February 1, 2011Date of Patent: January 28, 2014Assignee: Marvell World Trade Ltd.Inventors: Rony Ashkenazi, Alexander Zaslavsky, Gregory Uehara, Brian Brunn
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Patent number: 8565349Abstract: A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node.Type: GrantFiled: March 6, 2012Date of Patent: October 22, 2013Assignee: Marvell World Trade Ltd.Inventors: Brian Brunn, Gregory Uehara, Sehat Sutardja
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Patent number: 8532600Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.Type: GrantFiled: October 30, 2012Date of Patent: September 10, 2013Assignee: Marvell World Trade Ltd.Inventors: Gregory Uehara, Alexander Zaslavsky, Brian Brunn
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Patent number: 8520771Abstract: This disclosure describes techniques for modulating data. In one embodiment, these techniques include receiving an I or Q value, generating a time-shifted sample of a shaped pulse based on the I or Q value, and providing the time-shifted sample to a digital-to-analog converter.Type: GrantFiled: April 27, 2010Date of Patent: August 27, 2013Assignee: Marvell International Ltd.Inventors: Brian Brunn, Marc Leroux, Gregory Uehara
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Patent number: 8406358Abstract: A radio frequency (RF) apparatus has a receiver. The receiver includes a mixer, a clock generator, and a common mode controller. The clock generator couples to the mixer. The common mode controller couples to the outputs of mixer. The mixer, the clock generator and the common mode controller are operated collectively to program linearity and a gain of the receiver.Type: GrantFiled: February 17, 2009Date of Patent: March 26, 2013Assignee: Marvell International Ltd.Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
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Patent number: 8400197Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.Type: GrantFiled: July 26, 2011Date of Patent: March 19, 2013Assignee: Marvell World Trade Ltd.Inventors: Luca Romano, Alessandro Venca, Stefano Dal Toso, Antonio Milani, Brian Brunn
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Patent number: 8346179Abstract: An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric.Type: GrantFiled: May 3, 2010Date of Patent: January 1, 2013Assignee: Marvell World Trade Ltd.Inventors: Brian Brunn, Sehat Sutardja, Xiaohua Fan, Gregory Uehara