Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node.

Abstract: A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node.

Abstract: In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.

Abstract: In one embodiment, a voltage controlled oscillator (VCO) includes a tank circuit having a first node and a second node. A first pair of transistors includes a first transistor and a second transistor each having a gate, a drain, and a source. The gates of the first transistor and the second transistor are coupled together and coupled to the first node. A second pair of transistors includes a third transistor and a fourth transistor each having a gate, a drain, and a source. The gates of third transistor and the fourth transistor are coupled together and coupled to the second node. The first transistor and the second transistor are configured to alternately couple the second node to a first output node. The third transistor and the fourth transistor are configured to alternately couple the first node to a second output node.

Abstract: A method includes receiving a signal using a direct conversion receiver, while the receiver is set at a gain that is selected from a range of possible gain values. Multiple DC offset correction values are provided for use by a DC offset cancellation loop, each DC offset correction value being associated with a respective sub-range of the range of the possible gain values. A DC offset correction value is selected from among the multiple DC offset correction values based on the gain to which the receiver is set. A DC offset in the signal is canceled by setting the DC offset cancellation loop to the selected DC offset correction value.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

Abstract: An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric.

Abstract: Aspects of the disclosure can provide a bandpass transconductance amplifier that can include a minuend transconductance amplifier that converts a voltage signal to a first current and a subtrahend transconductance amplifier that converts the voltage signal to a second current having substantially the same amplitude as the first current but opposite polarity in both a first and a second stopband. The second current can have a substantially smaller amplitude than the first current in a passband. The disclosed bandpass transconductance amplifier can also include a controller that can tune the passband and the stopbands and a summing circuit that can add the first current and the second current.

Abstract: Aspects of the disclosure can provide a bandpass transconductance amplifier that can include a minuend transconductance amplifier that converts a voltage signal to a first current and a subtrahend transconductance amplifier that converts the voltage signal to a second current having substantially the same amplitude as the first current but opposite polarity in both a first and a second stopband. The second current can have a substantially smaller amplitude than the first current in a passband. The disclosed bandpass transconductance amplifier can also include a controller that can tune the passband and the stopbands and a summing circuit that can add the first current and the second current.

Abstract: A system includes an input node, a frequency translatable impedance (FTI) filter, and a radio frequency (RF) downconverter module. The input receives an input signal having first and second components. The FTI filter filters the second components. The RF downconverter module receives the first components and downconverts the first components. Both the FTI filter and the RF downconverter module communicate with the input node.

Abstract: Adjustment circuitry in a phase-locked loop (PLL) adjusts a sampling point to any desired location within a bit period of each bit of received high-speed serial data. The adjustment circuitry, responsive to program control, selectively adds current portions to a charge pump error current output thereby adjusting a feedback signal frequency to shift the serial data sampling point. A plurality of current mirror devices is scaled, with respect to a reference current device, to provide ?I current portions. A current control module controls the current portions magnitude and a sign of the current portions. The adjustment circuitry further controls charge pump programmable current sources in order to set a desired operating point of the PLL. The programmable current sources are controlled by a bias voltage and a plurality of selectable serial and parallel coupled resistors.

Abstract: Bit-Edge Zero Forcing Equalizer. A novel solution is presented by which a BE-ZFE (Bit-Edge Zero Forcing Equalizer) is employed to drive an error term within a data signal to an essentially zero value. This new BE-ZFE looks at values of data that occur at the bit edges of a data signal and drives the associated error term to zero. The new BE-ZFE is appropriately implemented within communication systems that are phase (or jitter) noise limited. Some examples of such communication systems include high-speed serial links one type of which serviced using a SERDES (Serializer/De-serializer) where data that is originally in a parallel format is serialized into a serial data stream and then subsequently de-serialized back into a parallel data stream.