Abstract: A method includes a plurality of voltage regulators distributing power to a plurality of components within a compute node, wherein each of the voltage regulators has a controller, volatile memory and non-volatile memory. The controller of each voltage regulator temporarily caches operating data for the voltage regulator in the volatile memory of the voltage regulator, wherein the controller temporarily caches the operating data collected from the voltage regulator over a sliding time period. When a first voltage regulator from among the plurality of voltage regulators experiences a fault event, the controller of each voltage regulator detects the fault event and automatically copies the cached operating data for the voltage regulator from the volatile memory of the voltage regulator to the non-volatile memory of the voltage regulator in response to detecting the fault event.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: A DC-DC converter includes a directly coupled inductor with coil elements and power-switching phases. Each phase includes a high-side and low-side switch, where the high-side switch couples a voltage source to a coil element and the low-side switch couples the coil element to a ground voltage. Each switch is configured to be alternately activated and no two switches are activated at the same time. A current sensor for the DC-DC converter includes a single current amplifier having inputs and an output. The output provides a current sensing signal. The current sensor also includes a single RC network coupled to one of the power-switching phases and a first input of the current amplifier. The current sensor also includes a resistive ladder. The ladder includes, for each of the other power-switching phases, a resistor coupled in parallel to the RC network resistor and to a second input of the current amplifier.

Abstract: A method includes performing operations on a compute node including a plurality of processors each having a local PCI processing element and a local processor interconnect, wherein the local processor interconnect of each processor is connected to the local processor interconnect of at least one other processor. The method further includes identifying a PCI device that is directly attached to the local PCI processing element of a first one of the processors and positioned in an upstream airflow direction from the first processor. The operating system monitors the PCI device and, in response to determining that the PCI device is performing a power-intensive operation, directs operations away from the first processor to a second one of the processors, wherein the local processor interconnect of the second processor is directly connected to the processor interconnect of the first processor.

Abstract: An apparatus for encrypting processor related noise is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a frequency selection module that selects frequencies for a first noise output. The frequencies are within a range of frequencies of a second noise output. The second noise output is produced by one or more first voltage regulating modules providing power to a processor. The apparatus includes an amplitude selection module that selects an amplitude for each frequency of the first noise output. The apparatus includes a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module. The first noise output combines with the second noise output to produce a third noise output such that coherence between the third noise output and operations of the processor is below a threshold.

Abstract: A method for controlling a voltage regulator includes monitoring an output current and an inductance of an output inductor in a voltage regulator, wherein the voltage regulator includes high-side and low-side field effect transistors both coupled to an input to the first output inductor. The high-side and low-side field-effect transistors are alternately turned on at a switching frequency, wherein only one of the field-effect transistors is turned on at a time. The method measures a change in the inductance of the output inductor resulting from the output inductor reaching current saturation and measures a rate of change in the output current of the output inductor. The switching frequency is controlled as a function of the measured change in the inductance and the measured rate of change in the output current in order to prevent an amount of current through the high-side field-effect transistor from exceeding a maximum operating current setpoint.

Abstract: An apparatus for encrypting processor related noise is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a frequency selection module that selects frequencies for a first noise output. The frequencies are within a range of frequencies of a second noise output. The second noise output is produced by one or more first voltage regulating modules providing power to a processor. The apparatus includes an amplitude selection module that selects an amplitude for each frequency of the first noise output. The apparatus includes a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module. The first noise output combines with the second noise output to produce a third noise output such that coherence between the third noise output and operations of the processor is below a threshold.

Abstract: According to one exemplary embodiment, a method for reducing electrical component stress from power cycling is provided. The method may include receiving an indication associated with power cycling an electronic apparatus. The method may also include identifying, based on the received indication, a first one or more groups of electrical components that will not be powered off during the power cycling of the electronic apparatus. The method may further include identifying, based on the received indication, a second one or more groups of electrical components that will be powered off during the power cycling of the electronic apparatus. The method may finally include powering off the second one or more groups of electrical components.

Abstract: According to one exemplary embodiment, a method for load optimization using cable-associated voltage drop is provided. The method may include receiving a plurality of tasks for processing by a plurality of electronic devices. The method may also include determining a power loss value for one or more power cables powering each of the plurality of electronic devices. The method may further include assigning the plurality of tasks to one or more of the plurality of electronic devices based on the power loss value for the one or more power cables powering each of the plurality of electronic devices.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes identifying a location of each of a plurality of installed memory modules present in the memory system. Still further, the method includes identifying a voltage sense line pair that provides a shortest aggregate distance to each of the installed memory modules, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the enable signal line, which includes a fuse. However, a fault protection circuit coupled to the enable signal line can pull down the enable signal line in response to a fault, such that the fuse is permanently opened. Once the fuse is open, the external power supply cannot be enabled and further damage to the computer planar is prevented.

Abstract: A method for controlling the in-rush current to a hot plug device. The method includes providing a series of turn on pulses to the gates of a plurality of turn on FETs on a hot plug device coupled to a direct current power source, wherein each pulse causes the plurality of FETs to pass current from the direct current power source to a subsystem of the hot plug device, and wherein each pulse has a duration that ends before the impedance of the turn on FETs falls below a safe operating region. The method further includes providing a steady turn on signal to the FETs in response to the output voltage from the FETs to a subsystem of the hot plug device exceeding a predetermined voltage threshold.

Abstract: A computer program product for controlling the in rush current to a hot plug device. The computer program product includes program instructions that cause a processor to perform a method. The method includes providing a series of turn on pulses to the gates of a plurality of turn on FETs on a hot plug device coupled to a direct current power source, wherein each pulse causes the plurality of FETs to pass current from the direct current power source to a subsystem of the hot plug device, and wherein each pulse has a duration that ends before the impedance of the turn on FETs falls below a safe operating region. The method further includes providing a steady turn on signal to the FETs in response to the output voltage from the FETs to a subsystem of the hot plug device exceeding a predetermined voltage threshold.

Abstract: A transversely actuated piezoelectric bellows heatsink (TAPBH) has a linkage that includes multiple rigid sections coupled by flexible joints. A first fixed support is affixed to a first end of the linkage, and a piezoelectric element is mechanically coupled to a second end of the linkage. A diaphragm is mechanically affixed to a first side of the linkage, and an air enclosure, having an open area, is affixed to the diaphragm. A second fixed support is mechanically affixed to a second side of the linkage. Cyclic power from the power supply causes the piezoelectric element to expand and contract to force the linkage to expand and contract in an analogous manner, thus causing the diaphragm to move in an amplified motion to cause air to enter and be expelled from the air enclosure via air valves.

Abstract: A method includes regulating voltage to a memory system responsive to a voltage signal received at a voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations within the memory system. The method further includes sequentially passing a voltage signal from each of the voltage sense line pairs to the voltage feedback line, and, for each voltage sense line pair, calculating a memory margin of the memory system based on memory operation while regulating voltage to the memory system responsive to the voltage signal from the voltage sense line pair. Still further, the method includes identifying the voltage sense line pair that provides the greatest memory margin, and then regulating voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: A computer program product includes a computer readable storage medium embodying program instructions executable by a processor to perform a method. The method includes sequentially passing a voltage signal from each voltage sense line pair to a voltage feedback line of a voltage regulator. The voltage regulator controls voltage to the memory system responsive to the voltage signal received at the voltage feedback line, wherein the memory system includes a plurality of voltage sense line pairs in different locations. For each voltage sense line pair, the method identifies a memory margin based on memory operation while regulating voltage responsive to the voltage signal from the voltage sense line pair. The voltage sense line pair that provides the greatest memory margin is identified, and the voltage regulator is made to control voltage to the memory system responsive to the identified voltage sense line pair.

Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.