Abstract: Controlling power consumption of a voltage regulator in a computer system that includes computer memory and the voltage regulator is configured to provide regulated source voltage to the computer memory includes: receiving, by a voltage regulator controller, memory margin statistics of the computer memory, the memory margin statistics including data describing operational tolerance of the computer memory to source voltage signal variations; and adjusting, by the voltage regulator controller, one or more operating characteristics of the voltage regulator in dependence upon the memory margin statistics.

Abstract: A method includes obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: Systems and methods for allocating memory usage based on voltage regulator efficiency are disclosed. According to an aspect, a method may include receiving a first efficiency value of a first voltage regulator associated with a first memory device among multiple memory devices. The method may also include receiving a second efficiency value of a second voltage regulator associated with a second memory device of the memory devices. The method may also include receiving a request to write data to one of the first memory devices and the second memory device. The method may also include determining whether to write the data to the first memory device or the second memory device based on the first and second efficiency values. Further, the method may include writing the data to the first memory device or the second memory device based on the determination.

Abstract: A computer program product includes a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by a processor to cause the processor to perform a method. The method comprises obtaining an activity level for each of a plurality of functions of an integrated circuit, wherein each function has a different physical location on the integrated circuit. The method further includes dynamically adjusting an amount of current supplied to the integrated circuit by each of a plurality of power stages of a DC voltage regulator to meet the current requirements of the plurality of functions and to control power losses between the power stages and the functions, wherein each power stage has a different physical location along a perimeter of the integrated circuit.

Abstract: A method of controlling the inrush current to a hot plug device. The method includes directing current from an input power rail of the hot plug device to an output power rail of the hot plug device through a high impedance auxiliary current path, wherein an electronic subsystem of the hot plug device is coupled to the output power rail. The method further includes allowing current from the input power rail to pass through a plurality of main turn on FETs to the output power rail in response to the output power rail having a voltage that exceeds a voltage threshold as a result of directing current through the high impedance auxiliary current path.

Abstract: A method for controlling the in-rush current to a hot plug device. The method includes providing a series of turn on pulses to the gates of a plurality of turn on FETs on a hot plug device coupled to a direct current power source, wherein each pulse causes the plurality of FETs to pass current from the direct current power source to a subsystem of the hot plug device, and wherein each pulse has a duration that ends before the impedance of the turn on FETs falls below a safe operating region. The method further includes providing a steady turn on signal to the FETs in response to the output voltage from the FETs to a subsystem of the hot plug device exceeding a predetermined voltage threshold.

Abstract: A transversely actuated piezoelectric bellows heatsink (TAPBH) has a linkage that includes multiple rigid sections coupled by flexible joints. A first fixed support is affixed to a first end of the linkage, and a piezoelectric element is mechanically coupled to a second end of the linkage. A diaphragm is mechanically affixed to a first side of the linkage, and an air enclosure, having an open area, is affixed to the diaphragm. A second fixed support is mechanically affixed to a second side of the linkage. Cyclic power from the power supply causes the piezoelectric element to expand and contract to force the linkage to expand and contract in an analogous manner, thus causing the diaphragm to move in an amplified motion to cause air to enter and be expelled from the air enclosure via air valves.

Abstract: A computer planar includes an enable signal line for providing an enable signal to an external power supply, wherein the external power supply will not turn on unless the enable signal is active high. During normal operation, an auxiliary power source maintains an active high enable signal on the enable signal line, which includes a fuse. However, a fault protection circuit coupled to the enable signal line can pull down the enable signal line in response to a fault, such that the fuse is permanently opened. Once the fuse is open, the external power supply cannot be enabled and further damage to the computer planar is prevented.

Abstract: According to one exemplary embodiment, a method for load optimization using cable-associated voltage drop is provided. The method may include receiving a plurality of tasks for processing by a plurality of electronic devices. The method may also include determining a power loss value for one or more power cables powering each of the plurality of electronic devices. The method may further include assigning the plurality of tasks to one or more of the plurality of electronic devices based on the power loss value for the one or more power cables powering each of the plurality of electronic devices.

Abstract: According to one exemplary embodiment, a method for reducing electrical component stress from power cycling is provided. The method may include receiving an indication associated with power cycling an electronic apparatus. The method may also include identifying, based on the received indication, a first one or more groups of electrical components that will not be powered off during the power cycling of the electronic apparatus. The method may further include identifying, based on the received indication, a second one or more groups of electrical components that will be powered off during the power cycling of the electronic apparatus. The method may finally include powering off the second one or more groups of electrical components.

Abstract: A hot plug device includes an electronic subsystem and a plurality of main turn on FETs, wherein each main turn on FET includes a gate, a power input for coupling to a power source, and an output for controllably providing power to the electronic subsystem. An auxiliary current path is in parallel with the main turn on FETs and includes a fuse, an impedance element and an auxiliary turn on FET. A turn on controller controls the main turn on FETs and the auxiliary turn on FET. Current is initially through the high impedance auxiliary current path to apply voltage to an output power rail. Subsequently, current is allowed to pass through a plurality of main turn on FETs to the output power rail in response to the output power rail having a voltage exceeding a voltage threshold as a result of using the high impedance auxiliary current path.

Abstract: A method control the in rush current to the hot plug device. The method includes providing a series of turn on pulses to the gates of a plurality of turn on FETs on a hot plug device coupled to a direct current power source, wherein each pulse causes the plurality of FETs to pass current from the direct current power source to a subsystem of the hot plug device, and wherein each pulse has a duration that ends before the impedance of the turn on FETs falls below a safe operating region. The method further includes providing a steady turn on signal to the FETs in response to the output voltage from the FETs to a subsystem of the hot plug device exceeding a predetermined voltage threshold.

Abstract: A method of determining power fault information using a voltage regulator-down (VRD) device having a fault-pin output is provided. The method may include receiving a fault indication from one of a plurality of fault detection devices, correlating the received fault indication with a timing signal having a predetermined time duration, applying a voltage change on the fault-pin output of the VRD device for the predetermined time duration corresponding to the timing signal, and applying the voltage change on the fault-pin output to a plurality of fuses. Based on the predetermined time duration associated with the applied voltage change, the plurality of fuses may be blown according to a binary pattern indicative of a fault type associated with the fault indication.