Patents by Inventor Brian D. Sawyer

Brian D. Sawyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7361987
    Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: April 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Patent number: 6921975
    Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126,326) may be electrically conductive or electrically non-conductive.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: July 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Patent number: 6838776
    Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Publication number: 20040207077
    Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Publication number: 20040207068
    Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: George R. Leal, Jie-Hua Zhao, Edward R. Prack, Robert J. Wenzel, Brian D. Sawyer, David G. Wontor, Marc Alan Mangrum
  • Publication number: 20030006062
    Abstract: Embodiments of the present invention relate generally to interconnect systems. One embodiment relates to an interconnect system having a first substrate, and a standoff that extends from said first substrate. The interconnect system further includes a cap, intended for subsequent reflow attachment, that covers a first end of the standoff and does not cover the sides of the standoff. The interconnect system further includes a nonwettable surface layer on the sides of the standoff such that the cap is prevented from substantially wetting the sides of the standoff when the cap is in a fluid state. The interconnect system may further include a second substrate attached to the cap where substantially all of the cap is located at the first end of the standoff. Another embodiment of the present inventions relates to a method of fabricating the interconnect system.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 9, 2003
    Inventors: William M. Stone, Trent Uehling, Brian D. Sawyer, Douglas G. Mitchell