Abstract: The invention constitutes a unique hardware zero overhead interrupt and task change mechanism for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) register, the invention uses one or more auxiliary latches (3, 4) wherein one latch (3, 4) is used as the “running” latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate “running” registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks.

Abstract: A portable holder for storing air guns and other hand tools is disclosed. In a preferred embodiment, the holder comprises: a generally-tubular body having two open ends, one of which is flared; a slit or gullet on one side of the body and extending longitudinally from the flared open end of the body partway down the body; and a plurality of magnetic discs or feet for removably, yet securely attaching the holder to a workstation having a ferrous surface. A related process for storing such tools comprises: orienting a generally tubular holder adjacent a workstation's metal side; removably affixing the holder to that metal surface by at least one magnet; slipping the particular tool into a flared end of the holder; and guiding a portion of the tool, such as an attached air hose or the tool handle, into a gullet of the holder to rest the tool and orient the hose or handle for easy retrieval of the tool from the holder.

Abstract: A method for the orderly execution of multiple tasks in a data processing system and a circuit for implementing that method include a plurality of task modules which construct bids based upon the order of the task and its priority. The highest priority highest order number tasks are switched to available system execution resources. The system permits the orderly execution of round-robin task sets in an environment of dynamically changing priorities. When a round-robin task set is interrupted, the system is able to return to the round-robin task set after execution of the higher priority task at the exact point the interruption occurred.

Abstract: A versatile book is disclosed for hanging pneumatically actuated devices (e.g., airguns or spray guns). In the preferred embodiment, the versatile hook comprises: a hook body having a base with an annular section that defines a through-space corresponding to the shape of the pneumatic device's cylindrical extension tube or barrel; a hook-shaped extension attached to the body; and, positioning-and-mounting means for selectively positioning the hook, around and along the barrel, and thereafter mounting the body in a temporarily fixed position onto the barrel, with the hook-shaped extension facing towards or away from the discharge nozzle. Upon loosening a bolt, the preferred hook can be reoriented.

Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

Abstract: A method for the orderly execution of multiple tasks in a data processing system and a circuit for implementing that method include a plurality of task modules which construct bids based upon the order of the task and its priority. The highest priority highest order number tasks are switched to available system execution resources. The system permits the orderly execution of round-robin task sets in an environment of dynamically changing priorities. When a round-robin task set is interrupted, the system is able to return to the round-robin task set after execution of the higher priority task at the exact point the interruption occurred.

Abstract: Systems and methods are described for pulse communications using precision timing. A method includes digitally pulse coding a data stream; and modulating a carrier signal using the digitally pulse coded data stream.

Abstract: Methods and devices for providing dialysis treatment are provided. The device includes a resin bed including zirconium phosphate, zirconium oxide, and urease.

Abstract: The invention constitutes a unique hardware zero overhead interrupt and task change system for the reduction or elimination of interrupt latency and task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) register, the invention uses one or more auxiliary latches (3, 4) wherein one latch (3, 4) is used as the "running" latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate "running" registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for the mandatory sequential execution of the linked tasks.