Patents by Inventor Brian Doyle

Brian Doyle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Semiconductor device structures and methods of forming semiconductor structures

Publication number: 20070001173

Abstract: A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane.

Type: Application

Filed: June 21, 2005

Publication date: January 4, 2007

Inventors: Justin Brask, Jack Kavalieros, Uday Shah, Suman Datta, Amlan Majumdar, Robert Chau, Brian Doyle
Strained field effect transistors

Publication number: 20060292776

Abstract: An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.

Type: Application

Filed: June 27, 2005

Publication date: December 28, 2006

Inventors: Been-Yih Jin, Robert Chau, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Markus Kuhn, Marko Radosavlievic, M. Shaheed, Patrick Keys
Metal gate device with reduced oxidation of a high-k gate dielectric

Publication number: 20060284271

Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

Type: Application

Filed: June 21, 2005

Publication date: December 21, 2006

Inventors: Brian Doyle, Jack Kavalieros, Justin Brask, Matthew Mertz, Mark Doczy, Suman Datta, Robert Chau
Method for fabricating transistor with thinned channel

Publication number: 20060286755

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Type: Application

Filed: June 15, 2005

Publication date: December 21, 2006

Inventors: Justin Brask, Robert Chau, Suman Datta, Mark Doczy, Brian Doyle, Jack Kavalieros, Amlan Majumdar, Matthew Metz, Marko Radosavljevic
Methods and apparatus for analysis of opportunities for marketing and providing of mortgage services

Publication number: 20060282371

Abstract: Systems and techniques for identifying and evaluating opportunities for marketing and providing mortgage services. Categories of demographic and economic data are identified that are required to provide specified information identifying comparative geographic regions and population groups with respect to opportunities they present for marketing and providing mortgage services. Arrangements are made to receive data as needed from one or more data sources supplying such data. Requirements specifying desired information are identified, and specific data and processing needed to generate information meeting the requirements is identified. The identified data is retrieved and processed and the information generated is formatted and presented.

Type: Application

Filed: June 8, 2005

Publication date: December 14, 2006

Applicant: GE Mortgage Holdings, LLC

Inventors: Brian Doyle, Erik Pollack, Michael Homiak, Mary Still
Method and apparatus for improving stability of a 6T CMOS SRAM cell

Publication number: 20060281236

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

Type: Application

Filed: August 21, 2006

Publication date: December 14, 2006

Inventors: Suman Datta, Brian Doyle, Robert Chau, Jack Kavalieros, Bo Zheng, Scott Hareland
Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Publication number: 20060267093

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Type: Application

Filed: May 4, 2006

Publication date: November 30, 2006

Inventors: Stephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Brian Doyle, Suman Datta, Vivek De
Compensating for induced strain in the channels of metal gate transistors

Publication number: 20060237801

Abstract: Strained channel field effect transistors may have a threshold voltage shift. This threshold voltage shift may be compensated for by adjusting channel doping. But this also adversely affects mobility. The threshold voltage shift may be compensated, without adversely affecting mobility, by tailoring the workfunction of a metal gate electrode used in the transistor to adequately compensate for that threshold voltage shift. For example, in some embodiments, an appropriate metal may be selected with a slightly higher workfunction or, in other cases, the workfunction of a selected metal may be adjusted by, for example, doping the metal gate electrode with a material which increases the workfunction of the gate electrode.

Type: Application

Filed: April 20, 2005

Publication date: October 26, 2006

Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau
Tri-gate devices and methods of fabrication

Publication number: 20060228840

Abstract: The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Type: Application

Filed: December 7, 2005

Publication date: October 12, 2006

Inventors: Robert Chau, Brian Doyle, Jack Kavalieros, Douglas Barlage, Suman Datta, Scott Hareland
Semiconductor device with a high-k gate dielectric and a metal gate electrode

Publication number: 20060220090

Abstract: A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed over a channel that is positioned within a substrate, and a metal gate electrode that is formed on the high-k gate dielectric layer. The high-k gate dielectric layer has off-state leakage characteristics that are superior to those of a silicon dioxide based gate dielectric, and on-state mobility characteristics that are superior to those of a high-k gate dielectric that comprises an isotropic material.

Type: Application

Filed: March 23, 2005

Publication date: October 5, 2006

Inventors: Matthew Metz, Suman Datta, Mark Doczy, Jack Kavalieros, Justin Brask, Brian Doyle, Marko Radosavljevic, Robert Chau
CARBON NANOTUBE ENERGY WELL (CNEW) FIELD EFFECT TRANSISTOR

Publication number: 20060220074

Abstract: A structure to form an energy well within a Carbon nanotube is described. The structure includes a doped semiconductor region and an undoped semiconductor region. The Carbon nanotube is between the doped semiconductor region and the undoped semiconductor region. The structure also includes a delta doped semiconductor region. The undoped semiconductor region is between the Carbon nanotube and the delta doped region. The delta doped semiconductor region is doped opposite that of the doped semiconductor region.

Type: Application

Filed: March 31, 2005

Publication date: October 5, 2006

Inventors: Suman Datta, Marko Radosavljevic, Brian Doyle, Jack Kavalieros, Justin Brask, Amlan Majumdar, Robert Chau
Self-aligned contacts for transistors

Publication number: 20060223302

Abstract: Self-aligned contacts for transistors and methods for fabricating the contacts are described. An etch resistant material is patterned to create an opening that resides above a transistor gate structure. A selective etch is performed through the opening that does not etch the transistor gate structure but does etch material that resides laterally with respect to the transistor gate structure in order to expose tops, immediately adjacent to the transistor gate structure, of drain and source regions of a diffusion layer of the transistor. Conductive material is deposited that covers respective tops of the drain and source regions of the diffusion layer of the transistor to a depth that does not short the drain and source region of the diffusion layer of the transistor. A layer above the conductive material is formed.

Type: Application

Filed: March 31, 2005

Publication date: October 5, 2006

Inventors: Peter Chang, Brian Doyle
Nonplanar device with thinned lower body portion and method of fabrication

Publication number: 20060214231

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Type: Application

Filed: May 23, 2006

Publication date: September 28, 2006

Inventors: Uday Shah, Brian Doyle, Justin Brask, Robert Chau, Thomas Letson
Field effect transistor with metal source/drain regions

Publication number: 20060202266

Abstract: A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.

Type: Application

Filed: March 14, 2005

Publication date: September 14, 2006

Inventors: Marko Radosavljevic, Suman Datta, Brian Doyle, Jack Kavalieros, Justin Brask, Mark Doczy, Amian Majumdar, Robert Chau
Creation of high mobility channels in thin-body SOI devices

Publication number: 20060205178

Abstract: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Type: Application

Filed: May 8, 2006

Publication date: September 14, 2006

Inventors: Brian Doyle, Brian Roberds
Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Publication number: 20060205167

Abstract: A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si1-xGex. The highest layer may be of the form Si1-yGey on the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form Si1-zGez on the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Type: Application

Filed: March 11, 2005

Publication date: September 14, 2006

Inventors: Jack Kavalieros, Justin Brask, Mark Doczy, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau, Everett Wang, Philippe Matagne, Lucian Shifren, Been Jin, Mark Stettler, Martin Giles
Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Patent number: 7098507

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Type: Grant

Filed: June 30, 2004

Date of Patent: August 29, 2006

Assignee: Intel Corporation

Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Brian Doyle, Suman Datta, Vivek K. De
Creation of high mobility channels in thin-body SOI devices

Publication number: 20060189096

Abstract: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film=and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Type: Application

Filed: April 13, 2006

Publication date: August 24, 2006

Inventors: Brian Doyle, Brian Roberds
Method for making a semiconductor device having a high-k gate dielectric

Publication number: 20060189156

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer that contacts a metal oxide layer. The metal oxide layer is generated by forming a metal layer, then oxidizing the metal layer.

Type: Application

Filed: February 23, 2005

Publication date: August 24, 2006

Inventors: Mark Doczy, Jack Kavalieros, Justin Brask, Matthew Metz, Suman Datta, Brian Doyle, Robert Chau
Metal gate carbon nanotube transistor

Publication number: 20060180859

Abstract: A top metal gate carbon nanotube transistor may be provided which has acceptable electrical characteristics. The transistor may be formed over a structure including a semiconductor substrate made of an epitaxial layer and covered with an insulating layer. The carbon nanotubes may be deposited thereover, source and drains defined, and a metal gate electrode applied over a high dielectric constant gate dielectric. The processing may be such that the carbon nanotubes are protected from high temperature processing and excessively oxidizing atmospheres.

Type: Application

Filed: February 16, 2005

Publication date: August 17, 2006

Inventors: Marko Radosavljevic, Amlan Majumdar, Suman Datta, Jack Kavalieros, Brian Doyle, Justin Brask, Robert Chau

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