Field effect transistor with metal source/drain regions
A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed adjacent the channel region on opposite sides of the gate electrode. The source and drain regions each comprise a semiconductor portion adjacent to and in contact with the semiconductor channel and a metal portion adjacent to and in contact with the semiconductor portion.
1. Field of the Invention
The present invention relates to the field of semiconductor devices and more particularly to a semiconductor device having a source/drain region comprising a semiconductor portion and a metal portion.
2. Discussion of Related Art
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of an ideal subthreshold gradient for optimized on-current/off-current ratios. An example of an proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in
The present invention is a field effect transistor with metal source/drain regions and its method of fabrication. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. In other instances, well known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
In embodiments of the present invention, include a metal oxide semiconductor field effect transistor having a pair of source/drain regions which each comprise a semiconductor portion and a metal portion. In an embodiment of the present invention, a replacement source/drain technique is used to etch away a portion of the doped source/drain regions so that they can be replaced with a high conductivity metal, such as platinum and palladium. In this way, a lower R-external may be achieved since the metallic interconnect extends much closer towards the channel region. In an embodiment of the present invention, the metal portion of the source/drain region is made extremely close to the channel region such that the metal is formed adjacent to and in contact with the tip or source/drain extension portion of the source and drain regions. By forming the source region and drain region with a metal portion and a semiconductor portion allows for the scalable switching of the PNP or NPN junctions while bringing the high conductivity metal source/drain electrodes as close to the channel region as possible. In this way, the metal source and drain regions can extend all the way to the tips of the transistor enhancing the external conductivity while circumventing known disadvantages of metal source/drains in direct contact with the channel material (e.g., ambipolar conduction). Although the source/drain structure of the present invention is ideally suited for use in very small width and narrow transistors, such as nonplanar devices, the present invention can be utilized in any transistor where its small size or dimensions causes the transistor to have a high R-external.
An example of a transistor 200 having source/drain regions with metal portions in accordance with an embodiment of the present invention is illustrated in
A source region 212 and a drain region 214 are formed in the semiconductor body 204 on opposite sides of the gate electrode 208 as shown in
As shown in
In an embodiment of the present invention, as illustrated in
In an embodiment of the present invention, isolation regions 307 are formed on insulating substrate 202 in order to isolate transistor 200 from adjacent transistors formed on substrate 202. Isolation regions 307 can be formed from an insulating oxide film, such as silicon dioxide. In an embodiment of the present invention, the metal portion 216 of the source region 212 and the metal portion 220 of the drain region 214 are formed in contact with isolation region 306 as well as in contact with the source and drain extension regions 304 and 306, respectively.
In an embodiment of the present invention, the source region 212 further includes a source contact region 314 and a drain contact region 316 formed in semiconductor body 204. The source and drain contact regions 314 and 316 are heavily doped regions. Heavily doped contact region 314 and 316 are doped to the same conductivity type as the source and drain extensions 304 and 306, but are typically doped to a higher concentration level. In an embodiment of the present invention, the source and drain contact region have a doping concentration between 1e20-1e21/cm3. The heavily doped source and drain contact region 314 and 316 are formed between the source/drain extension regions 304 and 306, and the metal portions 216 and 220 as illustrated in
Gate electrode 208 can be formed of any suitable gate electrode material. In an embodiment of the present invention, gate electrode 208 comprises a polycrystalline silicon doped to a concentration density between 1×1019 to 1×1020 atom/cm3. In an embodiment of the present invention, the gate electrode can be a metal gate electrode, such as but not limited to tungsten, tantalum, titanium and their nitrides. In an embodiment of the present invention, the gate electrode is formed from a material having a midgap work function between 4.6 to 4.8 eV. It is to be appreciated, that gate electrode 208 need not necessarily be a single material and can be a composite stack of thin films, such as but not limited to a polycrystalline silicon/metal electrode or a metal/polycrystalline silicon electrode.
Semiconductor body 204 can be formed of any well known semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SixGey), gallium arsenide (GaAs), InSb, GaP, GaSb, and carbon nanotubes. Semiconductor body 204 can be formed of any well known material which can be reversely altered from an insulating state to a conductive state by applying external electrical controls. Semiconductor body 204 is ideally a single crystalline film when the best electrical performance of transistor 200 is desired. For example, semiconductor body 204 is a single crystalline film when transistor 200 is used in high performance applications, such as a high density circuit, such as microprocessors. Semiconductor body 204, however, can be a polycrystalline film when transistor 200 is used in applications requiring less stringent performance, such as in liquid crystal displays.
In an embodiment of the present invention, substrate 202 is an insulating substrate which includes a lower monocrystalline silicon substrate 201 upon which is formed in insulating layer 203, such as silicon dioxide film. Transistor 200, however, can be formed on any well known insulating substrate, such as a substrate formed from silicon dioxide, nitrides, oxides and sapphires. In an embodiment of the present invention, substrate 202 can be a semiconductor substrate, such as but not limited to a monocrystalline silicon substrate and a gallium arsenide substrate.
In an embodiment of the present invention, the channel region 210 is intrinsic or undoped monocrystalline silicon. In an embodiment of the present invention, the channel region 210 is doped monocrystalline silicon. When channel region 210 is doped, it is typically doped to a conductivity level between 1×1016 to 1×1019 atom/cm3. When channel region 210 is doped, it is typically doped to the opposite conductivity type of the doped semiconductor portion of the source region 212 and the doped semiconductor portion drain region 214.
Gate dielectric layer 206 is formed on and around the sides of semiconductor body 204 as shown in
A method of fabricating a field effect transistor with source and drain regions having metal portions in accordance with embodiments of the present invention is illustrated in
In an embodiment of the present invention, semiconductor film 408 is an intrinsic (i.e., undoped) silicon film. In other embodiments, semiconductor film 408 is doped to a p type or n type conductivity with a concentration level between 1×1016 to 1×1019 atoms/cm3. Semiconductor film 408 can be insitu doped (i.e., doped while it is deposited) or doped after it is formed on substrate 402 by, for example, ion implantation. Doping after formation enables both PFET and NFET devices to be fabricated easily on the same insulating substrate. The doping level of the semiconductor film 408 determines the doping level of the channel region of the device. In an embodiment of the present invention, semiconductor film 408 is formed to a thickness which is approximately equal to the height desired for the subsequently formed semiconductor body or bodies of the fabricated transistor. In embodiments of the present invention, semiconductor film 408 has a thickness or height 409 of less than 30 nanometers and ideally less than 20 nanometers. In an embodiment of the present invention, semiconductor film 408 is formed to a thickness approximately equal to the gate “length” desired of the fabricated transistor. In an embodiment of the present invention, semiconductor film 408 is formed thicker than the desired gate length of the device. In an embodiment of the present invention, a semiconductor film 408 is formed to a thickness which will enable the fabricated transistor to be operated in a fully depleted manner for a desired gate length (Lg).
Semiconductor film 408 can be formed on insulating substrate 402 in any well known method. In one method of forming a silicon-on-insulator substrate, known as the “SIMOX” technique, oxygen atoms are implanted at a high dose into a single crystalline silicon substrate and then annealed to form the buried oxide 406 within the substrate. The portion of the single crystalline silicon substrate above the buried oxide becomes a silicon film. In another method an epitaxial silicon film transfer technique which is generally referred to as bonded SOI may be utilized to form a SOI substrate.
In an embodiment of the present invention, as shown in
Next, a semiconductor body 414 is formed from semiconductor film 408 as shown in
Next, as shown in
Next, as also shown in
Next, a pair of source/drain regions are formed in the semiconductor body 414 on opposite sides of gate electrode 418. As stated above, the source and drain regions each comprise a doped semiconductor portion and a metal portion. First, the semiconductor portions of the source/drain regions can be formed. In an embodiment of the present invention, the doped semiconductor portions include tip or source/drain extension regions. Source and drain extension regions 420 and 422 can be formed by placing dopants into the semiconductor body 414 on both sides of gate electrode 418 as shown in
Next, in an embodiment of the present invention, dielectric sidewall spacers 424 can be formed on the sidewalls of gate electrode 418. Sidewall spacers can be used to offset heavy source/drain contact implants. Spacers can be formed by blanket depositing a conformal dielectric film, such as but not limited to silicon nitride, silicon oxide, silicon oxynitride or combinations thereof over the substrate of
Next, if desired, heavy source/drain contact implants can be made to form heavily doped semiconductor film 414. Heavily doped source/drain contact regions can be formed by ion implantation with a vertical ion implantation process. The ion implantation process dopes the semiconductor body 414 located adjacent to the sidewall spacers to a concentration between 1×1020-1×1021 atoms/cm3 to form source contact region 426 and drain contact region 428. Sidewall spacers 424 offset the source/drain contact implantation step and define the tip regions as the regions of the doped semiconductor body 414 beneath sidewall spacers 424. The contact regions are the regions of the semiconductor body which are adjacent to the outside edges of the sidewall spacers 424.
Next, an interlayer dielectric (ILD) 430 is blanket deposited over the substrate as shown in
In an embodiment of the present invention, ILD 430 is formed of a material which can be selectively etched with respect to semiconductor body 414 so that an opening can be etched into the semiconductor body without laterally etching into ILD 430 adjacent to the sidewalls of the semiconductor body 414. In an embodiment of the present invention, interlayer dielectric 430 is formed from the same material, such as silicon dioxide, which is used to form isolation regions 410. In an embodiment of the present invention, after depositing interlayer dielectric 430, the dielectric layer can be planarized by, for example, chemical mechanical planarization in order to form the interlayer dielectric 430 with a planar top surface. Any suitable technique can be used to deposit the interlayer dielectric 430, such as but not limited to chemical vapor deposition (CVD) and high density plasma (HDP) CVD.
Next, as illustrated in 4I-4L, contact openings are etched through interlayer dielectric 430 and into semiconductor body 414 and then filled with a metal to form the metal portions of the source and drain regions. It is to be appreciated that
First, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as shown in
It is to be appreciated that although the present invention has been described with respect to a nonplanar transistor, such as a tri-gate transistor, the present invention is not to be limited to these types if transistors. For example, the present invention is equally applicable to the formation of source and drain regions of a planar transistor where the gate electrode and gate dielectric layer are formed on a single surface of semiconductor film as is well know in the art. Additionally, the present invention is equally applicable to FINFET devices or dual gate devices where the gate electrode/gate dielectric is formed on two sides of the semiconductor body and not on the top surface of the semiconductor body as is well known in the art.
Claims
1. A semiconductor device comprising:
- a gate electrode formed on a gate dielectric layer formed on a semiconductor channel region of a semiconductor film; and
- a pair of source/drain regions formed adjacent to said semiconductor channel region on opposite sides of said gate electrode, said source/drain regions comprising a semiconductor portion adjacent to and in contact with said semiconductor channel and a metal portion adjacent to and in contact with said semiconductor portion.
2. The semiconductor device of claim 1 wherein said semiconductor is silicon and said metal portion is platinum.
3. The semiconductor device of claim 1 wherein said semiconductor is carbon nanotubes and said metal portion is palladium.
4. The semiconductor device of claim 1 wherein said semiconductor channel region is formed on an insulating film of an insulating substrate and wherein said metal portion is formed on said insulating film.
5. The semiconductor device of claim 1 wherein said gate dielectric layer is formed on a first surface of said substrate and wherein said metal portion of said source/drain region is formed beneath said first surface.
6. The semiconductor device of claim 1 further comprising a pair of sidewall spacers formed adjacent to said gate electrode wherein a portion of said metal portion of said source/drain regions is formed beneath said sidewall spacers.
7. The semiconductor device of claim 6 wherein said silicon portion of said source/drain regions is formed beneath said sidewall spacers.
8. A semiconductor device comprising:
- a semiconductor body formed on an oxide film formed on a substrate, said semiconductor body having a top surface and a pair of laterally opposite sidewalls;
- a gate dielectric layer formed on the top surface and sidewalls of said semiconductor body;
- a gate electrode formed on said gate dielectric layer on said top surface of said semiconductor body and on said sidewalls of said semiconductor body, said gate electrode having a pair of laterally opposite sidewalls;
- a pair of sidewall spacers formed adjacent to said laterally opposite sidewalls of said gate electrode and on said top surface of said semiconductor body and adjacent to said sidewalls of said semiconductor body;
- a pair of source/drain regions each comprising: a source/drain extension formed in said semiconductor body beneath said sidewalls spacers; and a metal portion in contact with said source/drain extension.
9. The semiconductor device of claim 8 wherein said metal portion is in contact with said oxide film formed on said substrate.
10. The semiconductor device of claim 8 wherein said metal portion extends beneath said pair of sidewall spacers.
11. The semiconductor device of claim 8 wherein said metal portion is formed from a metal selected from the group consisting of palladium and platinum.
12. The semiconductor device of claim 8 wherein said semiconductor body is silicon and wherein said metal portion is platinum.
13. The semiconductor device of claim 8 wherein said semiconductor body is carbon nanotubes and said metal portion is palladium.
14. A method of forming a semiconductor device comprising:
- forming a gate electrode on a gate dielectric layer formed on a channel region of a semiconductor film;
- forming a pair of source/drain regions on opposite sides of said gate electrode wherein said source/drain regions comprise a semiconductor portion adjacent to and in contact with said channel region and a metal portion adjacent to and in contact with said semiconductor portion.
15. The method of claim 14 further comprising forming a pair of sidewall spacers adjacent to the sidewalls of said gate electrode; and
- forming said semiconductor portion of said source/drain regions beneath said pair of sidewall spacers.
16. The method of claim 14 wherein said semiconductor film is silicon and said metal portion is platinum.
17. The method of claim 14 wherein said semiconductor film is carbon nanotubes and said metal portion is palladium.
18. A method of forming a transistor comprising:
- forming a gate electrode having a pair of laterally opposite sidewalls on a gate dielectric layer formed on a semiconductor layer;
- forming a pair of source/drain extensions in said semiconductor layer on opposite sides of said gate electrode;
- forming a pair of sidewall spacers adjacent to said sidewalls of said gate electrode and on said source/drain extensions;
- forming a pair of source/drain contact regions in said semiconductor layer on opposite sides of said sidewall spacers;
- forming an interlayer dielectric adjacent to said sidewall spacers and over said source/drain contact regions;
- etching a pair of contact openings through said interlayer dielectric to expose a portion of said source/drain contact regions;
- etching away a portion of said source/drain contact regions to form a pair of etched-out source/drain contact regions; and
- depositing a metal film into said contact openings and into said etched-out source/drain contact regions.
19. The method of claim 18 wherein said metal film in said etched-out source/drain contact regions directly contact said source/drain extensions.
20. The method of claim 18 wherein said metal film is formed beneath said sidewall spacers.
21. The method of claim 18 wherein said source/drain extensions are formed by ion implanting dopants in alignment with said sidewalls of said gate electrode.
22. The method of claim 18 wherein said source/drain contact regions are formed by ion implanting dopants into said semiconductor film in alignment with the outside edges of said sidewall spacers.
23. A method of forming a nonplanar transistor comprising:
- forming a semiconductor body having a top surface opposite a bottom surface formed on an insulating layer of an insulating substrate, said semiconductor body having a pair of laterally opposite sidewalls;
- forming a gate dielectric layer on the top surface and sidewalls of said semiconductor body;
- forming a gate electrode having a pair of laterally opposite sidewalls on said gate dielectric layer and on the top surface of said semiconductor body and adjacent to said gate dielectric layer on said sidewalls of said semiconductor body;
- forming a pair of source/drain extensions in said semiconductor body on opposite sides of said gate electrode;
- forming a pair sidewalls spacers adjacent to said gate electrode and on and adjacent to said source/drain extensions formed in said semiconductor body;
- forming a pair of source/drain contact regions in said semiconductor body on opposite sides of said sidewall spacers;
- forming an interlayer dielectric layer over and adjacent to said semiconductor body and adjacent to said sidewall spacers;
- etching a pair of contact openings through said interlayer dielectric layer to said source/drain contact regions in said semiconductor body;
- etching away a portion of said source/drain contact regions in said semiconductor body; and
- depositing a metal film in said contact openings and in said etched away portion of said semiconductor body.
24. The method of claim 23 wherein said etching of said portion of said source/drain contact region in said semiconductor body etches until said insulating layer of said insulating substrate is reached.
25. The method of claim 24 wherein said metal film in said etched away portion of said semiconductor body contact said source/drain extension regions.
26. The method of claim 23 wherein said opening in said semiconductor body is larger than the contact opening formed through said interlayer dielectic.
Type: Application
Filed: Mar 14, 2005
Publication Date: Sep 14, 2006
Inventors: Marko Radosavljevic (Beaverton, OR), Suman Datta (Beaverton, OR), Brian Doyle (Portland, OR), Jack Kavalieros (Portland, OR), Justin Brask (Portland, OR), Mark Doczy (Beaverton, OR), Amian Majumdar (Portland, OR), Robert Chau (Beaverton, OR)
Application Number: 11/080,765
International Classification: H01L 29/772 (20060101); H01L 21/336 (20060101);