Patents by Inventor Brian E. Stine

Brian E. Stine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10897814
    Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 19, 2021
    Assignee: PDF Solutions, Inc.
    Inventor: Brian E. Stine
  • Publication number: 20200120791
    Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 16, 2020
    Inventor: Brian E. Stine
  • Patent number: 10517169
    Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 24, 2019
    Assignee: PDF SOLUTIONS, INC.
    Inventor: Brian E Stine
  • Publication number: 20190320525
    Abstract: A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.
    Type: Application
    Filed: October 16, 2018
    Publication date: October 17, 2019
    Inventor: Brian E. Stine
  • Patent number: 7673262
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: March 2, 2010
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 7494893
    Abstract: In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitored and collected as process tool data. Other information about the wafers, such as metrology data and product layout attribute, may also be collected. A model describing the relationship between the defectivity data and process tool data may be created and thereafter used to relate the process tool data to a yield of the process module. The model may initially be an initial model using process tool data from a limited number of test wafers that contain test structures. The model may also be an expanded model using process tool data from product wafers containing embedded test structures in areas with no product devices.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: February 24, 2009
    Assignee: PDF Solutions, Inc.
    Inventors: Anand Inani, Brian E. Stine, Marci Yi-Ting Liao, Senthil Arthanari, Michael V. Williamson, Spencer B. Graves, Guanyuan M. Yu
  • Publication number: 20080282210
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 13, 2008
    Applicant: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 7373625
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: May 13, 2008
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 7356800
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: April 8, 2008
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 7348594
    Abstract: A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb structure having a plurality of side walls. The tines of the first comb structure are positioned within side walls of the snake structure or second comb structure. The tines of the first comb structure are offset from a center of the side walls. Test data collected from the test structure are analyzed, to estimate product yield. The test structure may have a lower layer pattern, such that topographical variations of the lower layer pattern propagate to an upper layer pattern of the test structure.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: March 25, 2008
    Assignee: PDF Solutions, Inc.
    Inventors: Dennis J. Ciplickas, Brian E. Stine, Yanwen Fei
  • Patent number: 7305638
    Abstract: A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two candidate ROM design modifications are identified. At least one of the candidate ROM design modifications comprises inversion of bit values of data to be stored in the ROM. A plurality of criteria are applied, including at least an amount of yield improvement and a difficulty of implementation associated with each candidate ROM design modification. One of the candidate ROM design modifications is selected based on the application of the criteria. A modified ROM fabrication process is performed to fabricate a ROM according to the selected ROM design modification.
    Type: Grant
    Filed: May 13, 2005
    Date of Patent: December 4, 2007
    Assignee: PDF Solutions, Inc.
    Inventor: Brian E. Stine
  • Patent number: 7197726
    Abstract: A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: March 27, 2007
    Assignee: PDF Solutions, Inc.
    Inventors: Dennis J. Ciplickas, Markus Decker, Christopher Hess, Brian E. Stine, Larg H. Weiland
  • Patent number: 7174521
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: February 6, 2007
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 7154115
    Abstract: A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two parallel line segments connected by a perpendicular line segment. Each of the plurality of test pads is connected to a respective turn section of a respective one of the nested serpentine lines. Each pair of test pads connected to one of the subset of the nested serpentine lines has at least a respectively different turn section portion connected therebetween.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: December 26, 2006
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, Larg H. Weiland, Dennis J. Ciplickas
  • Patent number: 7024642
    Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a . . . 301h, 302a . . . 302h), each pair of nested serpentine lines having a shared pad between them (312a . . . 312h).
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: April 4, 2006
    Assignee: PDF Solutions, Inc.
    Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas
  • Patent number: 6901564
    Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: May 31, 2005
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 6834375
    Abstract: A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: December 21, 2004
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, Larg H. Weiland, Dennis J. Ciplickas, John Kibarian
  • Publication number: 20040232910
    Abstract: A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies with metal height. The second structure is a NEST structure (1000). Loop lines of the loop structure (1010) are connected on both sides of the NEST structure (1000).
    Type: Application
    Filed: July 16, 2004
    Publication date: November 25, 2004
    Inventors: Dennis J Ciplickas, Markus Decker, Christopher Hess, Brian E Stine, Larg H Weiland
  • Patent number: 6795952
    Abstract: A system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle (12) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model (16). The yield model (16) embodies a layout as defined by the characterization vehicle (12) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine (18) extracts predetermined layout attributes (26) from a proposed product layout (20).
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: September 21, 2004
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, David M. Stashower, Sherry F. Lee, Kurt H. Weiner
  • Publication number: 20040094762
    Abstract: A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a. . . 301h, 302a. . . 302h), each pair of nested serpentine lines having a shared pad between them (312a. . . 312h).
    Type: Application
    Filed: September 12, 2003
    Publication date: May 20, 2004
    Inventors: Christopher Hess, David Stashower, Brian E. Stine, Larg H. Weiland, Richard Burch, Dennis J. Ciplickas