Patents by Inventor Brian E. Stine

Brian E. Stine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030145292
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Application
    Filed: July 18, 2002
    Publication date: July 31, 2003
    Inventors: Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis, Purnendu K. Mozumder, Sherry F. Lee, Larg H. Weiland, Dennis J. Ciplickas, David M. Stashower
  • Patent number: 6475871
    Abstract: A test structure for analyzing failures due to fabrication induced defects in integrated circuits includes a matrix of bit cells formed by word lines and bit lines. An associated word line probe pad is electrically connected to each word line and an associated bit line probe pad electrically connected to each bit line. A test structure is electrically connected between a word line and a bit line of an associated bit cell. Each test structure has at least one variable attribute which is used to detect defects and create yield models.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 5, 2002
    Assignee: PDF Solutions, Inc.
    Inventors: Brian E. Stine, Christopher Hess, Larg H. Weiland
  • Patent number: 6449749
    Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: September 10, 2002
    Assignee: PDF Solutions, Inc.
    Inventor: Brian E. Stine