Abstract: Methods of fabricating structures, such as memory cell structures by exposing at least one edge portion of an intermediate nitride layer arranged between a polysilicon layer and a tungsten layer and performing an angled implant at the at least one edge portion to form a doped region through the at least one edge portion of the intermediate nitride layer is provided. The intermediate nitride layer may be formed by an anneal process, for example.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Abstract: Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of wordline stacks, a nitride layer may form between the polysilicon layer and the conductive metal layers above the polysilicon layer. While the nitride layer may be desirable during the fabrication process, it may inhibit electrical conductivity between the polysilicon layer and the conductive metal layers. A two step etch process may be implemented wherein the wordline stacks are etched into the polysilicon layer in the first etch and etched down to the substrate during the second etch. An angled implant may be used to break up the nitride layer between the first etch and the second etch.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Abstract: Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of wordline stacks, a nitride layer may form between the polysilicon layer and the conductive metal layers above the polysilicon layer. While the nitride layer may be desirable during the fabrication process, it may inhibit electrical conductivity between the polysilicon layer and the conductive metal layers. A two step etch process may be implemented wherein the wordline stacks are etched into the polysilicon layer in the first etch and etched down to the substrate during the second etch. An angled implant may be used to break up the nitride layer between the first etch and the second etch.

Abstract: Ion implantation may be used to break up a dielectric layer that forms during the fabrication of a memory array. More specifically, during the fabrication of wordline stacks, a nitride layer may form between the polysilicon layer and the conductive metal layers above the polysilicon layer. While the nitride layer may be desirable during the fabrication process, it may inhibit electrical conductivity between the polysilicon layer and the conductive metal layers. A two step etch process may be implemented wherein the wordline stacks are etched into the polysilicon layer in the first etch and etched down to the substrate during the second etch. An angled implant may be used to break up the nitride layer between the first etch and the second etch.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.

Abstract: A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.