Integrated circuitry
A silicon nitride comprising layer formed over a semiconductor substrate includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate thereto. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal. A substantially undoped silicon dioxide comprising layer formed over a semiconductor substrate includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate thereto. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal. Integrated circuitry is also disclosed.
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This patent resulted from a divisional application of U.S. patent application Ser. No. 09/924,816, filed Aug. 7, 2001 now U.S. Pat. No. 6,806,197, entitled “Method of Forming Integrated Circuitry, and Method of Forming a Contact Opening”, naming Shane J. Trapp and Brian F. Lawlor as inventors, the disclosure of which is incorporated by reference.
TECHNICAL FIELDThis invention relates to methods of forming integrated circuitry, to methods of forming contact openings, and to integrated circuitry.
BACKGROUND OF THE INVENTIONSemiconductor processing often involves the deposition of films or layers over or on a semiconductor substrate surface which may or may not have other layers already formed thereon. In typical circuitry fabrication, portions of an outer layer are masked, typically using photoresist, to provide a desired pattern over the outer layer. An underlying layer is then removed by chemical etching through the mask opening, with the mask covering and protecting other areas from the etching. Often it is desirable to etch an outer layer or layers selectively relative to an underlying layer. Accordingly, materials on the substrate, etch chemistry and conditions are continually being developed and improved to achieve a manner by which the desired layer(s) can be etched while stopping and substantially not etching an underlying layer.
Also, some layers are removed by mechanical polishing action or by chemical mechanical polishing action. In many such instances, it is also desirable to remove one or more layers while stopping on some immediately underlying layer.
SUMMARYThe invention includes methods of forming integrated circuitry, methods of forming contact openings, and integrated circuitry. In one implementation, a silicon nitride comprising layer is formed over a semiconductor substrate. The silicon nitride comprising layer includes Al, Ga or a mixture thereof. A silicon dioxide comprising layer is formed proximate the silicon nitride comprising layer. The silicon dioxide comprising layer is removed substantially selectively relative to the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the removal.
In one implementation, a substantially undoped silicon dioxide comprising layer is formed over a semiconductor substrate. The substantially undoped silicon dioxide comprising layer includes B, Al, Ga or mixtures thereof. A doped silicon dioxide comprising layer is formed proximate the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer, with the B, Al, Ga or mixtures thereof enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removal.
In one implementation, integrated circuitry includes a pair of spaced conductive device components received over a substrate, with such at least partially defining a node location there between. Each device component has at least one sidewall which faces the other device component of the pair. An insulative material mass is received over each of the sidewalls. The masses are laterally spaced from one another in a non-contacting relationship. The masses comprise a first insulative material comprising B, Al, Ga or mixtures thereof. A conductive contact is received between the insulative material masses in electrical connection with the node location.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
Exemplary preferred embodiments of forming integrated circuitry are initially described with reference to
A pad oxide layer 14 is formed over semiconductor substrate 12. A silicon nitride comprising layer 16 is formed over pad oxide layer 14 and semiconductor substrate 12. An exemplary thickness range for layer 14 is from 50 Angstroms to 150 Angstroms, while an exemplary thickness range for layer 16 is from 400 Angstroms to 1200 Angstroms. Silicon nitride comprising layer 16 has an outer surface 18.
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Regions 20/20a might, of course, in the depicted first exemplary embodiment, be formed prior to or subsequent to fabrication of the exemplary opening 22. Further, in one preferred embodiment, silicon nitride comprising layer 16 with enriched region 20/20a can be annealed prior to the removing action. Such might be desirable to facilitate migration of the gallium or aluminum to bond sites within silicon nitride comprising layer 16. Any alternate or additional fabrication is also contemplated in the context of the accompanying claims.
In one implementation, the invention also contemplates forming integrated circuitry comprising forming a substantially undoped silicon dioxide comprising layer over a semiconductor substrate. At least one enriched region analogous to regions 20 and 20a in the above-described first preferred silicon nitride comprising layer embodiment is formed within the substantially undoped silicon dioxide comprising layer. The enriched region comprises B, Al, Ga or mixtures thereof. An exemplary diffusion species for Boron is diborane, while an exemplary implant species for boron is B11. A doped silicon dioxide comprising layer is formed proximate, and more preferably on, the substantially undoped silicon dioxide comprising layer. The doped silicon dioxide comprising layer is removed substantially selectively relative to the substantially undoped silicon dioxide comprising layer. The at least one enriched region preferably enhances selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again, removing is preferably by chemical etching, with removal by polishing or other techniques also of course being contemplated. By way of example only, an exemplary process for etching doped silicon dioxide selectively relative to substantially undoped silicon dioxide where region 20 facilitates selectivity in the etch includes a 12 Liter Applied Materials 5000 Etch Chamber, operated at 1000W, 50 mtorr, Ar flow at 120 sccm, CF4 flow at 30 sccm, CHF3 flow at 50 sccm, and CH2F2 flow at 15 sccm.
The above-described preferred embodiments are associated with forming respective enriched regions within the subject layers. However, in one aspect, the invention also more generically contemplates forming a silicon nitride comprising layer also comprising Al, Ga or a mixture thereof. Such Al, Ga or a mixture thereof might be present in the silicon nitride comprising layer as an enriched region, as described in the above preferred embodiments, or such might be substantially homogeneously distributed within the silicon nitride comprising layer, with the Al, Ga or a mixture thereof enhancing selectivity to the silicon nitride comprising layer during the subject removing.
With respect to a substantially undoped silicon dioxide comprising layer, the invention also more generically contemplates B, Al, Ga or mixtures thereof being present within the substantially undoped silicon dioxide comprising layer, with such enhancing selectivity to the substantially undoped silicon dioxide comprising layer during the removing. Again by way of example only, the B, Al, Ga or mixtures thereof might be present as an enriched region or portion thereof, or might be substantially homogeneously distributed within the substantially undoped silicon dioxide comprising layer.
By way of example only, alternate preferred embodiments of the invention are described with reference to
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The above-described preferred embodiments are only exemplary in connection with methodical aspects of the invention, which are only limited by the accompanying claims as literally worded and as interpreted in accordance with the doctrine of equivalents. The invention also contemplates integrated circuitry independent of the method of fabrication as literally claimed without limitation to the preferred depicted embodiments, and as interpreted in accordance with the doctrine of equivalents.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims
1. Integrated circuitry comprising:
- a pair of spaced and adjacent conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material comprising Ga and Al; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
2. The integrated circuitry of claim 1 wherein the Ga and Al are substantially homogeneously distributed within the insulative masses.
3. The integrated circuitry of claim 1 wherein the insulative masses comprises B.
4. The integrated circuitry of claim 1 wherein the device components comprise field effect transistor gates.
5. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material comprising Al, Ga or a mixture thereof, the insulative material further comprising B; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
6. The integrated circuitry of claim 5 wherein the device components comprise field effect transistor gates.
7. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material and having a respective lateral outer enriched insulative material region comprising Al, Ga or a mixture thereof which has greater quantity of said Al, Ga or mixture thereof as compared to another region of said insulative mass; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
8. The integrated circuitry of claim 7 wherein the device components comprise field effect transistor gates.
9. The integrated circuitry of claim 7 wherein the insulative masses comprise anisotropically etched sidewall spacers.
10. The integrated circuitry of claim 7 wherein the insulative masses comprise bases and tops, the bases being wider than the tops.
11. The integrated circuitry of claim 7 wherein the insulative masses have lateral outer surfaces, the outer enriched regions extending to at least a portion of the lateral outer surfaces.
12. The integrated circuitry of claim 7 wherein the insulative material comprises substantially undoped silicon dioxide.
13. The integrated circuitry of claim 7 wherein the insulative material comprises silicon nitride.
14. The integrated circuitry of claim 7 wherein the conductive contact is received on the insulative masses.
15. The integrated circuitry of claim 7 wherein the enriched region comprises Al.
16. The integrated circuitry of claim 7 wherein the device components comprise field effect transistor gates.
17. The integrated circuitry of claim 7 wherein the another region is received immediately laterally inward of the lateral outer enriched region.
18. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material and having a respective lateral outer enriched region comprising Al, Ga or a mixture thereof, the insulative material further comprising B; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
19. The integrated circuitry of claim 18 wherein the enriched region is electrically insulative.
20. The integrated circuitry of claim 18 wherein the device components comprise field effect transistor gates.
21. The integrated circuitry of claim 18 wherein the enriched region comprises Al.
22. The integrated circuitry of claim 18 wherein the enriched region comprises Ga.
23. The integrated circuitry of claim 18 wherein the enriched region comprises Al and Ga.
24. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material and having a respective lateral outer enriched region comprising Ga which has greater quantity of Ga as compared to another region of said insulative mass that is received immediately laterally inward thereof; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
25. The integrated circuitry of claim 24 wherein the enriched region is electrically insulative.
26. The integrated circuitry of claim 24 wherein the device components comprise field effect transistor gates.
27. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material and having a respective lateral outer enriched region comprising at least two of B, Al, and Ga; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
28. The integrated circuitry of claim 27 wherein the enriched region comprises B, Al, and Ga.
29. The integrated circuitry of claim 28 wherein the enriched region is electrically insulative.
30. The integrated circuitry of claim 27 wherein the enriched region is electrically insulative.
31. The integrated circuitry of claim 27 wherein the device components comprise field effect transistor gates.
32. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship. the masses comprising an insulative material and having a respective lateral outer enriched region comprising Ga and Al which has greater guantity of Ga as compared to another region of said insulative mass; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
33. The integrated circuitry of claim 32 wherein the enriched region is electrically insulative.
34. The integrated circuitry of claim 32 wherein the another region is received immediately laterally inward of the lateral outer enriched region.
35. Integrated circuitry comprising:
- a pair of spaced conductive device components comprising field effect transistor gates received over a substrate, and a node location therebetween, each field effect transistor gate having at least one sidewall which faces the other field effect transistor gate of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material comprising Ga and Al; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
36. The integrated circuitry of claim 35 the Ga and Al are substantially homogeneously distributed within the insulative masses.
37. The integrated circuitry of claim 35 wherein the insulative masses comprises B.
38. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material and having a respective lateral outer enriched insulative material region comprising Al, Ga or a mixture thereof, the insulative masses having lateral outer surfaces, the outer enriched regions extending to only a portion of the lateral outer surfaces; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
39. The integrated circuitry of claim 38 wherein the device components comprise field effect transistor gates.
40. The integrated circuitry of claim 38 wherein the enriched region comprises Al.
41. The integrated circuitry of claim 38 wherein the enriched region comprises Ga.
42. The integrated circuitry of claim 38 wherein the enriched region comprises Al and Ga.
43. Integrated circuitry comprising:
- a pair of spaced conductive device components received over a substrate, and a node location therebetween, each device component having at least one sidewall which faces the other device component of the pair;
- an insulative mass received over each of said sidewalls, the masses being laterally spaced from one another in a non-contacting relationship, the masses comprising an insulative material comprising Ga and B; and
- a conductive contact received between the insulative masses in electrical connection with the node location.
44. The integrated circuitry of claim 13 wherein the device components comprise field effect transistor gates.
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Type: Grant
Filed: Mar 18, 2003
Date of Patent: Nov 6, 2007
Patent Publication Number: 20030203628
Assignee: Micron Technology, Inc. (Boise, ID)
Inventors: Shane J. Trapp (Boise, ID), Brian F. Lawlor (Boise, ID)
Primary Examiner: Jerome Jackson
Assistant Examiner: Paul Budd
Attorney: Wells St. John P.S.
Application Number: 10/391,952
International Classification: H01L 29/12 (20060101);