Patents by Inventor Brian G. Drost

Brian G. Drost has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10530368
    Abstract: A clock circuit includes a circuit configured to use a regulated voltage on a regulated voltage node to provide a frequency modulated clock signal having a frequency vacillating between a first frequency and a second frequency. The clock circuit includes an auxiliary loading circuit coupled to the regulated voltage node and configured to selectively provide load compensation for a load difference of the circuit. The load difference is a difference between a first load corresponding to the first frequency and a second load corresponding to the second frequency. The circuit may include a frequency divider circuit configured to use the regulated voltage on the regulated voltage node to generate the frequency modulated clock signal by frequency dividing an input clock signal according to a divide value vacillating between a first divide value and a second divide value.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 7, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20200006314
    Abstract: An array of capacitors on an integrated circuit includes a plurality of unit capacitors. Each unit capacitor includes an isolated capacitor node formed in a pillar structure. Each unit capacitor further includes a shared capacitor adjacent to the isolated capacitor node. The shared capacitor node is electrically coupled to shared capacitor nodes of other unit capacitors in the array. Each unit capacitor further includes a shield node coupled to a low impedance node and formed adjacent to the isolated capacitor node to reduce the chance of capacitance forming between conductors to the isolated nodes and the shared nodes thereby preventing unwanted charge from entering the shared nodes and reducing linearity of the array.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20200007136
    Abstract: A time-to-voltage converter is configured to generate an output voltage signal and a correlated reference voltage signal. The time-to-voltage converter includes a current source configured to generate a bias current through a current source output node. The time-to-voltage converter includes a first switched-capacitor circuit coupled to the current source output node and configured to generate the output voltage signal based on an input time signal and the bias current during a first interval. The time-to-voltage converter includes a second switched-capacitor circuit coupled to the current source output node and configured to generate the correlated reference voltage signal based on a reference time signal and the bias current during a second interval. The first interval and the second interval are non-overlapping intervals.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Inventors: Aaron J. Caffee, Jeffrey L. Sonntag, Brian G. Drost, Volodymyr Kratyuk
  • Patent number: 10523211
    Abstract: A divider includes ? divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A ? divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: December 31, 2019
    Assignee: Silicon Laboratories Inc.
    Inventor: Brian G. Drost
  • Patent number: 10498352
    Abstract: A method for reducing data-dependent loading on a voltage reference pre-charges a capacitor of the capacitive digital-to-analog converter to configure the capacitor in a pre-charged state during a first interval. The method selectively discharges the capacitor from the pre-charged state according to a value of an input digital signal to configure the capacitor in a selectively discharged state during a second interval. The method holds an output node of the capacitive digital-to-analog converter at a reset voltage level during the first interval and the second interval. The output node is coupled to a first terminal of the capacitor. The method discharges any remaining charge on the capacitor and providing an output voltage signal to an output node of the capacitive digital-to-analog converter according to the selectively discharged state during a third interval. The output voltage signal has a voltage level corresponding to a value of the input digital signal.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 3, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Volodymyr Kratyuk
  • Publication number: 20190305783
    Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.
    Type: Application
    Filed: April 3, 2018
    Publication date: October 3, 2019
    Inventors: Aaron J. Caffee, Russell Croman, Brian G. Drost
  • Patent number: 10153084
    Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: December 11, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Patent number: 10044383
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 7, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Alessandro Piovaccari, Aslamali A. Rafi
  • Publication number: 20180190424
    Abstract: A technique for forming an integrated circuit including an inductor reduces magnetic coupling between the inductor and surrounding elements. The technique includes deliberate placement of circuit elements (e.g., terminals, pins, routing traces) in locations on the integrated circuit relative to a magnetic vector potential associated with the inductor and relative to a magnetic flux density field associated with the inductor to reduce or eliminate induced signals that degrade system performance.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 5, 2018
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20180191384
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Aaron J. Caffee, Brian G. Drost, Alessandro Piovaccari, Aslamali A. Rafi
  • Patent number: 10008981
    Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 26, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Hendricus de Ruijter
  • Patent number: 9979404
    Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 22, 2018
    Assignee: Silicon Laboratories Inc.
    Inventors: Brian G. Drost, Aaron J. Caffee, Alessandro Piovaccari, Aslamali A. Rafi
  • Publication number: 20180054203
    Abstract: A divider includes 2/3 divider stages that may be turned off without toggling to extend the divide range of the divider while also reducing the impact of spurs on the divider output, and preserving the timing margin to update the divide ratio glitchlessly. A 2/3 divider stage responds to an input enable signal being deasserted and a modulus input signal being asserted to remain in a disabled state in which the divider stage does not toggle by ensuring storage elements outputs in the divider stage remain constant. The divider further selects an update clock for the divide ratio of the divider utilizing an output from a most downstream stage that remains enabled.
    Type: Application
    Filed: August 17, 2016
    Publication date: February 22, 2018
    Inventor: Brian G. Drost
  • Patent number: 9804573
    Abstract: A time-to-digital converter utilizes both coarse and fine quantizers and addresses mismatch by using redundant bits in the coarse time representation and the fine time representation. The redundant bits are compared and if the redundant bits are the same, no mismatch correction is required but if the redundant bits are different a correction is applied to correct the redundant portion of the coarse time information. The redundant portion includes the most significant bit generated by the fine quantizer and the least significant bit of the coarse quantizer. The correction adds to or subtracts from the redundant information.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 31, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Brian G. Drost, Ankur Guha Roy
  • Patent number: 9698807
    Abstract: A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 4, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Volodymyr Kratyuk
  • Patent number: 9634678
    Abstract: A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 25, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost, Vaibhav Karkare
  • Patent number: 9531394
    Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 27, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Publication number: 20160373120
    Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Aaron J. Caffee, Brian G. Drost
  • Patent number: 9509278
    Abstract: An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 29, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Jeffrey L. Sonntag, Brian G. Drost, Mehrnaz Motiee
  • Patent number: 9489000
    Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 8, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Aaron J. Caffee, Brian G. Drost