Abstract: A technique for on-chip time measurement includes dynamically scaling a range of a time-based digital-to-analog converter to enhance resolution of the time measurement. An apparatus includes a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock signal and a first digital code. The apparatus includes a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock signal and a second digital code. The first reference clock signal has a first frequency and the second reference clock signal has a second frequency that is harmonically related to the first frequency. The apparatus includes a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.

Abstract: A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.

Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

Abstract: An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode.

Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.

Abstract: An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

Abstract: A noise-shaping time-to-digital converter has a large range and high resolution. The time-to-digital converter includes a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal. The time-to-digital converter includes a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal. The time-to-digital converter includes an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code. The time-to-digital converter includes a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference signal and an enable signal. The time-to-digital converter includes a feedback circuit to generate the phase-adjusted feedback signal based on the reference signal and the gating signal.

Abstract: A technique for calibrating a digital-to-time converter includes an apparatus including a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration signal. The output signal has edges linearly delayed from corresponding edges of the input signal based on the digital code. The digital code vacillates between an evaluation code and a calibration code. The apparatus includes a reference signal generator configured to provide a delayed version of the input signal. The delay of the reference signal generator is matched to a delay of the digital-to-time converter. The apparatus includes a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version of the input signal. The calibration code may alternate between a first calibration delay code and a second calibration delay code.

Abstract: A digital-to-time converter includes a first node, a second node configured to receive a reference signal, and a digital-to-analog signal converter configured to couple a passive impedance to the first node. The passive impedance is selected according to the digital code. The digital-to-time converter also includes a first switch configured to selectively couple the first node to a second reference signal in response to the input signal and a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on the second node. The digital-to-time converter may include a second switch configured to selectively couple the first node to a third reference signal in response to a first control signal.

Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.

Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.

Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.

Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.

Abstract: A method of operating a system including a MEMS device of an integrated circuit die includes generating an indicator of a device parameter of the MEMS device in a first mode of operating the system using a monitor structure formed using a MEMS structural layer of the integrated circuit die. The method includes generating, using a CMOS device of the integrated circuit die, a signal indicative of the device parameter and based on the indicator. The device parameter may be a geometric dimension of the MEMS device. The method may include, in a second mode of operating the system, compensating for a difference between a value of the signal and a target value of the signal. The method may include re-generating the indicator after exposing the MEMS device to stress and generating a second signal indicating a change in the device parameter.

Abstract: An apparatus includes a microelectromechanical system (MEMS) device. The MEMS device includes a resonator suspended from a substrate, an anchor disposed at a center of the resonator, a plurality of suspended beams radiating between the anchor and the resonator, a plurality of first electrodes disposed about the anchor, and a plurality of second electrodes disposed about the anchor. The plurality of first electrodes and the resonator form a first electrostatic transducer. The plurality of second electrodes and the resonator form a second electrostatic transducer. The first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane of the substrate in response to a signal on the first electrode.

Abstract: A method of operating a programmable charge pump includes configuring each of a plurality of cascaded charge pump stages to be in a first set of charge pump stages or in a second set of charge pump stages based on an indicator of a target output voltage level. The first set of charge pump stages is configured to level-shift a first voltage level to a second voltage level. Each charge pump stage of the second set of charge pump stages has a disabled pump circuit portion. The second set of charge pump stages is configured to pass a version of the second voltage level to an output node of the programmable charge pump.

Abstract: A method of operating a programmable charge pump includes configuring each of a plurality of cascaded charge pump stages to be in a first set of charge pump stages or in a second set of charge pump stages based on an indicator of a target output voltage level. The first set of charge pump stages is configured to level-shift a first voltage level to a second voltage level. Each charge pump stage of the second set of charge pump stages has a disabled pump circuit portion. The second set of charge pump stages is configured to pass a version of the second voltage level to an output node of the programmable charge pump.