Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.

Abstract: A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.

Abstract: A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

Abstract: A micromechanical system (MEMS) acoustic wave resonator is formed on a base substrate. A piezoelectric member is mounted on the base substrate. The piezoelectric member has a first electrode covering a first surface of the piezoelectric member and a second electrode covering a second surface of the piezoelectric member opposite the first electrode, the second electrode being bounded by a perimeter edge. A first guard ring is positioned on the second electrode spaced apart from the perimeter edge of the second electrode.

Abstract: A method for creating a double Bragg mirror is provided. The method comprises providing a wafer having a plurality of bulk acoustic wave (BAW) devices at an intermediate stage of manufacturing. A first dielectric layer is deposited over the wafer. A plurality of as-deposited thicknesses of the dielectric layer are determined, each as-deposited thickness corresponding to one BAW device from the plurality of BAW devices. A corresponding trimmed dielectric layer over each of the BAW devices is formed by removing a portion of the dielectric layer over each of the BAW devices, with a thickness of the removed portion determined from a corresponding as-deposited thickness and a target thickness. A Bragg acoustic reflector that includes the corresponding trimmed dielectric layer is formed over each of the BAW devices.

Abstract: A method for creating a double Bragg mirror is provided. The method comprises providing a wafer having a plurality of bulk acoustic wave (BAW) devices at an intermediate stage of manufacturing. A first dielectric layer is deposited over the wafer. A plurality of as-deposited thicknesses of the dielectric layer are determined, each as-deposited thickness corresponding to one BAW device from the plurality of BAW devices. A corresponding trimmed dielectric layer over each of the BAW devices is formed by removing a portion of the dielectric layer over each of the BAW devices, with a thickness of the removed portion determined from a corresponding as-deposited thickness and a target thickness. A Bragg acoustic reflector that includes the corresponding trimmed dielectric layer is formed over each of the BAW devices.

Abstract: A micromechanical system (MEMS) acoustic wave resonator is formed on a base substrate. A piezoelectric member is mounted on the base substrate. The piezoelectric member has a first electrode covering a first surface of the piezoelectric member and a second electrode covering a second surface of the piezoelectric member opposite the first electrode, the second electrode being bounded by a perimeter edge. A first guard ring is positioned on the second electrode spaced apart from the perimeter edge of the second electrode.

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.

Abstract: A method of fabricating an integrated circuit (IC) includes providing a substrate having a semiconductor surface layer comprising an unpatterned resistive layer. Measurements are obtained of a characteristic of the unpatterned resistive layer at each of a plurality of locations over the substrate. The unpatterned resistive layer is modified, such as by targeted removal of layer material, in response to the measurements such that the measured characteristic is more uniform across the substrate. A resistor on the IC is defined from the unpatterned resistive layer after the modifying.

Abstract: In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Abstract: In described examples of a micromechanical system (MEMS), a rigid cantilevered platform is formed on a base substrate. The cantilevered platform is anchored to the base substrate by only a single anchor point. A MEMS resonator is formed on the cantilevered platform.

Abstract: A method of forming an integrated circuit includes forming ?1 hard mask layer on a device layer on a BOX layer of a SOI substrate. A patterned masking layer is used for a trench etch to simultaneously form larger and smaller area trenches through the hard mask layer, device layer and the BOX layer. A dielectric liner is formed for lining the larger and smaller area trenches. A dielectric layer is deposited for completely filling the smaller area trenches and only partially filling the larger area trenches. The larger area trenches are bottom etched through the dielectric layer to provide a top side contact to the handle portion. The handle portion at a bottom of the larger area trenches is implanted to form a handle contact, and the larger area trenches are completely filled with an electrically conductive layer to form a top side ohmic contact to the handle contact.

Abstract: A bulk acoustic wave (BAW) resonator includes a substrate having a top side surface and a bottom side surface. A Bragg mirror is on the top side surface of the substrate. A bottom electrode layer is on the Bragg mirror, and a piezoelectric layer is on the bottom electrode layer. A top dielectric layer is on the piezoelectric layer, and a top electrode layer is on the top dielectric layer. The bottom side surface of the substrate has a surface roughness of at least 1 ?m root mean square (RMS).

Abstract: A bulk acoustic wave (BAW) resonator includes a substrate having a top side surface and a bottom side surface. A Bragg mirror is on the top side surface of the substrate. A bottom electrode layer is on the Bragg mirror, and a piezoelectric layer is on the bottom electrode layer. A top dielectric layer is on the piezoelectric layer, and a top electrode layer is on the top dielectric layer. The bottom side surface of the substrate has a surface roughness of at least 1 ?m root mean square (RMS).

Abstract: A bulk acoustic wave (BAW) resonator includes a substrate having a top side surface and a bottom side surface. A Bragg mirror is on the top side surface of the substrate. A bottom electrode layer is on the Bragg mirror, and a piezoelectric layer is on the bottom electrode layer. A top dielectric layer is on the piezoelectric layer, and a top electrode layer is on the top dielectric layer. The bottom side surface of the substrate has a surface roughness of at least 1 ?m root mean square (RMS).

Abstract: A bulk acoustic wave (BAW) resonator includes a substrate having a top side surface and a bottom side surface. A Bragg mirror is on the top side surface of the substrate. A bottom electrode layer is on the Bragg mirror, and a piezoelectric layer is on the bottom electrode layer. A top dielectric layer is on the piezoelectric layer, and a top electrode layer is on the top dielectric layer. The bottom side surface of the substrate has a surface roughness of at least 1 ?m root mean square (RMS).

Abstract: A method of forming IC devices includes providing a substrate and forming a patterned masking layer including at least one masked region having at least one masking layer, and a feature region bounded by the masking layer. Etching forms an etched feature in the substrate, wherein undercutting during the etching forms at least one mask overhang region over a surface portion of the etched feature that is recessed relative to an outer edge of the masking layer. A pullback etch process exclusive of any additional patterning step laterally etches the masking layer. The conditions for the pullback etch retain at least a portion of the masking layer and reduce a length of the mask overhang region by at least 50%, or eliminate the mask overhang region entirely. The etched feature is then filled after the pullback etch process to form a filled etched feature.

Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.

Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.

Abstract: One aspect of the invention provides an integrated circuit (IC). The IC comprises transistors and contact fuses. The contact fuses each comprise a conducting layer, a frustum-shaped contact has a narrower end that contacts the conducting layer and a first metal layer that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink that is located over and contacts the first metal layer.