Abstract: A modular, multi-part roller skate is provided. The multi-part roller skate includes a roller skate body, a front wheel assembly, a rear wheel assembly, a support surface for supporting a footwear of a user, and at least one securing element for securing the footwear to the support surface. The multi-part roller skate is configurable as a modular roller skate with a removable pair of rear wheels, an interchangeable modular roller skate and ice skate, and an interchangeable modular roller skate and cross-country ski/snowshoe. In some embodiments, the multi-part roller skate can also be configured as a length-adjustable skate with a length adjustable skate body that includes separate front and rear foot support structures.

Abstract: A method for reducing emissions from a vessel includes isolating the vessel from a downstream fluid flow line, purging a fluid from the vessel by injecting purging media into the vessel to push the fluid through a check valve of a vent tubing and into the downstream fluid flow line, and draining the purging media from the vessel. A first end of the vent tubing is coupled to the housing of the vessel, and a second end of the vent tubing is coupled to the downstream fluid flow line. Further, the vent tubing includes a check valve disposed between the first end and the second end, and the check valve is configured to allow fluid to flow from the housing to the downstream fluid flow line.

Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.

Abstract: Substrate-free integrated circuit structures, and methods of fabricating substrate-free integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin, a plurality of gate structures over the fin, and a plurality of alternating P-type epitaxial structures and N-type epitaxial structures between adjacent ones of the plurality of gate structures.

Abstract: A method for reducing emissions from a vessel includes isolating the vessel from a downstream fluid flow line, purging a fluid from the vessel by injecting purging media into the vessel to push the fluid through a check valve of a vent tubing and into the downstream fluid flow line, and draining the purging media from the vessel. A first end of the vent tubing is coupled to the housing of the vessel, and a second end of the vent tubing is coupled to the downstream fluid flow line. Further, the vent tubing includes a check valve disposed between the first end and the second end, and the check valve is configured to allow fluid to flow from the housing to the downstream fluid flow line.

Abstract: A passenger seat assembly includes a first seat, a second seat, and a center console. In embodiments, a privacy divider is positioned atop the center console and serves as a mounting location for amenities for serving the first and second passenger seats. The center console is configurable to include various privacy, comfort, and utility features depending on the intended seating class for the passenger seat assembly. In embodiments, the first and second passenger seats include headrests and privacy assemblies associated with the headrests for enhancing privacy between the seats and/or relative to adjacent aisles.

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

Abstract: Substrate-less vertical diode integrated circuit structures, and methods of fabricating substrate-less vertical diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor fin in a dielectric layer, the semiconductor fin having a top and a bottom, and the dielectric layer having a top surface and a bottom surface. A first epitaxial semiconductor structure is on the top of the semiconductor fin. A second epitaxial semiconductor structure is on the bottom of the semiconductor fin. A first conductive contact is on the first epitaxial semiconductor structure. A second conductive contact is on the second epitaxial semiconductor structure.

Abstract: Disclosed herein are systems and methods for detecting foreign material in a good. A system controls an X-ray machine to capture an image of a good. The system analyzes the image captured by the X-ray machine by applying one or more of a foreign material detection algorithm and a foreign material model to the image. The system determines whether the good includes a foreign material comprising a challenge card by detecting at least one marking component on the foreign material when analyzing the image, wherein the challenge card includes the at least one marking component and a challenge material.

Abstract: A system and method for digital imaging and communications in security (DICOS) standard compliance validation. The system and method may validate both communication messages and files for compliance with the DICOS standard. In some embodiments, the system includes a processor for communicating with a test subject and a memory having program instructions stored thereon for performing a compliance test of the test subject to determine if the test subject is complaint with the DICOS standard. Execution of the instructions by the processor causes the processor to carry out the steps of: confirming that a transmitted DICOS message, e.g., a response or request, from the test subject is compliant with the DICOS standard; logging any errors in the transmitted DICOS message from the test subject in a validation report; and transmitting a simulated DICOS message, e.g., a response or request, to the test subject.

Abstract: An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

Abstract: A system and method for digital imaging and communications in security (DICOS) standard compliance validation. The system and method may validate both communication messages and files for compliance with the DICOS standard. In some embodiments, the system includes a processor for communicating with a test subject and a memory having program instructions stored thereon for performing a compliance test of the test subject to determine if the test subject is complaint with the DICOS standard. Execution of the instructions by the processor causes the processor to carry out the steps of: confirming that a transmitted DICOS message, e.g., a response or request, from the test subject is compliant with the DICOS standard; logging any errors in the transmitted DICOS message from the test subject in a validation report; and transmitting a simulated DICOS message, e.g., a response or request, to the test subject.

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.

Abstract: A modular, multi-part roller skate is provided. The multi-part roller skate includes a roller skate body, a front wheel assembly, a rear wheel assembly, a support surface for supporting a footwear of a user, and at least one securing element for securing the footwear to the support surface. The multi-part roller skate is configurable as a modular roller skate with a removable pair of rear wheels, an interchangeable modular roller skate and ice skate, and an interchangeable modular roller skate and cross-country ski/snowshoe. In some embodiments, the multi-part roller skate can also be configured as a length-adjustable skate with a length adjustable skate body that includes separate front and rear foot support structures.

Abstract: Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.

Abstract: Described herein are unmanned aerial vehicles (UAVs), systems, and methods for capturing panoramic images using cameras onboard a UAV. For example, an embodiment pertains to a UAV including a flight control system, a propulsion system operatively coupled with the flight control system, and an image system comprising navigational cameras and a gimbal camera. The image system is configured to capture a first set of images of a scene using the navigational cameras, stitch the first set of images together to create a first panoramic image of the scene, identify a flight plan for capturing a second set of images with which to create a second panoramic image of the scene using the gimbal camera, capture the second set of images of the scene using the gimbal camera, and stitch the second set of images together to create the second panoramic image.

Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.