Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.

Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.

Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. A period of time in which power cycling of the first hardware component takes place is shortened as the age of the first hardware component approaches the expected lifespan of the first hardware component. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.

Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.

Abstract: Provided are a computer program product, system, and method for recovering storage devices in a storage array having errors. A determination is made to replace a first storage device in a storage array with a second storage device. The storage array is rebuilt by including the second storage device in the storage array and removing the first storage device from the storage array resulting in a rebuilt storage array. The first storage device is recovered from errors that resulted in the determination to replace. Data is copied from the second storage device included in the rebuilt storage array to the first storage device. The recovered first storage device is swapped into the storage array to replace the second storage device in response to copying the data from the second storage device to the first storage device.

Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.

Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. A period of time in which power cycling of the first hardware component takes place is shortened as the age of the first hardware component approaches the expected lifespan of the first hardware component. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.

Abstract: A method for providing stable and reliable power to electronic devices is disclosed. In one embodiment, such a method includes providing a backplane having several power supplies coupled thereto. The method further provides connectors to connect multiple power-consuming devices, such as storage drives, expansion cards, memory expansion cards, or the like, to the backplane. In certain embodiments, the backplane provides a data transfer path and shared power distribution to the power-consuming devices. In the event a power supply is electrically decoupled from the backplane, the method enables a supplemental power-supplying device to supply power to the backplane by way of one of the connectors. A corresponding system is also disclosed.

Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.

Abstract: A method for providing stable and reliable power to electronic devices is disclosed. In one embodiment, such a method includes providing a backplane having several power supplies coupled thereto. The method further provides connectors to connect multiple power-consuming devices, such as storage drives, expansion cards, memory expansion cards, or the like, to the backplane. In certain embodiments, the backplane provides a data transfer path and shared power distribution to the power-consuming devices. In the event a power supply is electrically decoupled from the backplane, the method enables a supplemental power-supplying device to supply power to the backplane by way of one of the connectors. A corresponding system is also disclosed.

Abstract: For reducing lock contention on a Modified Least Recently Used (MLRU) list for metadata tracks, upon a conclusion of an access of a metadata track, if one of the metadata track is located in a predefined lower percentile of the MLRU list, and the metadata track has been accessed, including the access, a predetermined number of times, the metadata track is removed from a current position in the MLRU list and moved to a Most Recently Used (MRU) end of the MLRU list.

Abstract: An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair.

Abstract: For reducing lock contention on a Modified Least Recently Used (MLRU) list for metadata tracks, upon a conclusion of an access of a metadata track, if one of the metadata track is located in a predefined lower percentile of the MLRU list, and the metadata track has been accessed, including the access, a predetermined number of times, the metadata track is removed from a current position in the MLRU list and moved to a Most Recently Used (MRU) end of the MLRU list.

Abstract: An out-of-band to optical conversion component is provided that uses a transmit disable signal and a receive loss of signal (LOS) signal built into optical small form-factor pluggable transceiver and cable to pass the out-of-band protocol between serial attached. SCSI enclosures. The transmit disable signal, when asserted, turns off the optical output, while the receive LOS signal detects the loss of signal. The out-of-band to optical conversion component sits in line on the serial attached SCSI data traffic and strips off the out-of-band signals from the serial attached SCSI expander so that only data flows over the optical cable. The out-of-band to optical conversion component sends the out-of-band signals to the other enclosure using the transmit disable pin on the small form-factor pluggable transceiver and cable. The other enclosure receives the message on the receive LOS signal and transmit it back onto the serial attached SCSI receive data pair.

Abstract: A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port.

Abstract: A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed.

Abstract: A mechanism is provided for moving control of storage devices from one adapter pair to another. In a trunked disk array configuration, moving the storage devices from one disk array to another disk array begins by attaching the downstream ports of the two independent disk arrays together. The mechanism redefines one set of the ports as upstream ports and through switch zoning makes a set of devices available to the second disk array adapters. By controlling zoning access and performing discovery one device port at a time, the mechanism transfers access and ownership of the RAID group from one adapter pair to another.

Abstract: A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port.

Abstract: A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive.

Abstract: A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.