Abstract: A method is disclosed to set the signaling rate of a switch domain disposed in an information storage and retrieval system. The method establishes a switch domain target operating speed, and determines if that switch domain target operating speed comprises a first signaling rate. If the switch domain target operating speed comprises a first signaling rate, then the method asserts first Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using that first signaling rate. If the switch domain target operating speed does not comprise the first signaling rate, then the method asserts second Device Control Code bits to each of the plurality of data storage devices, and each of the plurality of data storage devices communicates with the switch using a second signaling rate.

Abstract: A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.

Abstract: A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

Abstract: Detecting excess current flow in a pluggable component is performed by completing a first current supply path between a power source and a pluggable component, and subsequently completing a second current supply path in parallel with the first current supply path. The first and second current supply paths form a current divider for supplying the pluggable component with electrical power from the power source. The first current supply path includes a current sensing mechanism for sensing current consumption of the pluggable component. The sensed current consumption is used to provide excess current detection for the pluggable component.

Abstract: A power supply system for reducing input ripple voltage, the system including: a first regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a second regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; a Nth regulator having at least two inputs, one input being a voltage input pin and another input being a synchronization pin; wherein outputs of the first regulator, second regulator, and Nth regulator are connected to a single power bus or correspondingly to separate power buses; a first delay connected to the synchronization pin of the second regulator; a second delay connected to the synchronization pin of the Nth regulator; wherein the first delay and the second delay have different delays configured for enabling the first regulator, second regulator, and the Nth regulator to operate out of phase; and a master clock for providing timing control to the first and second dela

Abstract: A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.

Abstract: A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

Abstract: Systems and methods for diagnosing faults in a multiple domain storage system. Exemplary embodiments include a system for diagnosing faults, the system including independent servers coupled to a serial attached SCSI switch module, end devices coupled to the serial attached SCSI module, at least one external cable connected between the serial attached SCSI module and the plurality of end devices, wherein the external cable defined an external fabric between the serial attached SCSI module and the plurality of end devices; and a process residing on the external fabric, the process having instructions to disable a high speed serializer/deserializer residing on each of the plurality of end devices, enable a universal asynchronous receiver/transmitter interface residing on each of the plurality of end devices, send and receive single ended data and in response to a complete data transfer, disabling the universal asynchronous receiver/transmitter interface and enabling the high speed serializer/deserializer.

Abstract: A power supply system for reducing input ripple voltage, the system including: a first switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; a second switching regulator having at least two input pins, one input pin being a voltage input pin and another input pin being a synchronization input pin; wherein outputs of the first switching regulator and the second switching regulator are connected to a power bus; a first delay element connected to the synchronization input pin of the first switching regulator; a second delay element connected to the synchronization input pin of the second switching regulator; wherein the first delay element and the second delay element have different delays, the first switching regulator and second switching regulator operating out of phase; and a master clock for providing timing control to the first and second delay elements.

Abstract: A method for reducing collisions within a plurality of networks, each of the plurality of networks having a plurality of workstations physically communicating over a plurality of shared communication channels, the method comprising: determining if a communication channel is available for transmitting data between the plurality of workstations; transmitting the data between all or part of the plurality of workstations via the communication channel; controlling the transmitted data between the plurality of workstations via a controller; monitoring the transmitted data by using a logic circuit; generating reverse polling of shared resources to reduce the collisions from occurring upon transmitting the data over the communication channel when a determination is made that at least two workstations of the plurality of workstations attempt to access a same shared resource within the plurality of networks; and notifying the controller of the reverse polling of the transmitted data and performing a low frequency time

Abstract: A data processing unit including a first active cooling device configured to respond to a first control signal and a second active cooling device configured to respond to a second control signal. The control signals may be any type of control signal suitable to control the operation of the first and second active cooling devices. The data processing unit also includes a first control function selectively capable of providing the first control signal and/or the second control signal, and a second control function selectively capable of providing the first control signal and/or the second control signal. Logic associated with the first and second control functions is included to determine which of the control functions will provide which control signal at a specific time. Logic and/or switching or isolation apparatus is also included to prevent both the first and second control functions from attempting to provide one of the control signals simultaneously.

Abstract: A multiple-master Inter Integrated Circuit (“I2C”) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.

Abstract: A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as priority or size of transaction. The invention allows connection of logical macros and prioritizes the appropriate operation for the resources available to optimize data throughput to optimize the utilization of multiple buses. A first arbiter manages data transmissions over a first communication bus. Arriving short or high-priority messages are transmitted over a second communication bus managed by a second arbiter, but only if the target logical macro is not the same as currently targeted by the first arbiter.

Abstract: A state machine is used to remove residual electric charge from a sense line and to sample the voltage of the sense line at multiple pre-determined times to determine the presence of a terminating capacitor and its value. Various values of capacitors identify discrete conditions. These discrete conditions may identify different types of plug-in cards or models of plug-in cards within a group type.