Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.

Abstract: This disclosure includes a method for securing a memory of an electronic system that includes initializing the memory, creating a security key, transmitting the security key to memory, storing the security key in the memory, transmitting the current security key and a a new security key to the memory by the memory controller. If the current security key transmitted is the same as the security key stored in memory, then access to the memory is enabled and the current security key in the memory is replaced with the new security key. If the current security key transmitted is not the same as the security key stored in the memory, then access to the memory is disabled.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals.

Abstract: A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.

Abstract: A method and circuit for implementing faster-cycle-time and lower-energy write operations for Synchronous Dynamic Random Access Memory (SDRAM), and a design structure on which the subject circuit resides are provided. A first RAS (row address strobe) to CAS (column address strobe) command delay (tRCD) is provided to the SDRAM for a read operation. A second delay tRCD is provided for a write operation that is substantially shorter than the first delay tRCD for the read operation.

Abstract: An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the rectangular printed circuit card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card.

Abstract: A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring the bit error rate (BER) in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the BER data at the local side to generate the remote side transmission characteristics for the link channel.

Abstract: Products comprising labile compounds, such as polyunsaturated fatty acids, and having first and second encapsulants are disclosed. A first encapsulant can be a spray dried coating and the second encapsulant can be a prill coating. Methods of making the same are provided.

Abstract: A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the eye characteristics of the channels used by the local side physical layer to transfer data to the remote side physical layer, transferring eye characteristics acquired in the monitoring to the local side physical layer and processing the eye characteristics by the local side physical layer to generate equalization setting adjustments.

Abstract: A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the bit error rate (BER) of the channels used by the local side physical layer to transfer data to the remote side physical layer, monitoring the BER in the channels used for data transfer, transferring BER data acquired in the monitoring to the local side physical layer and processing the BER data by the local side physical layer to generate equalization setting adjustments.

Abstract: A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring the bit error rate (BER) in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the BER data at the local side to generate the remote side transmission characteristics for the link channel.

Abstract: A method and accompanying system are disclosed for tuning each channel of a high-speed SerDes link interface arranged in a configuration linking a local side to a remote side. The method includes transmitting a flow control packets from the local side to the remote side to change remote side transmission characteristics in a link channel; monitoring signal eye characteristics in the link channel; transferring additional flow control packets to adjust the remote side transmission characteristics; and processing the signal eye characteristics at the local side to generate the remote side transmission characteristics for the link channel.

Abstract: Products comprising core materials, such as polyunsaturated fatty acids, encapsulated by an encapsulant formed from hydrolyzed protein having a degree of protein hydrolysis of between about 1% and about 15%, and from caramelization products, are disclosed. Methods of making the same and of making the encapsulant are also provided.

Abstract: A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the bit error rate (BER) of the channels used by the local side physical layer to transfer data to the remote side physical layer, monitoring the BER in the channels used for data transfer, transferring BER data acquired in the monitoring to the local side physical layer and processing the BER data by the local side physical layer to generate equalization setting adjustments.

Abstract: A method is disclosed for tuning each channel of a high-speed SerDes cable link interface arranged in a configuration linking a local side physical layer to a remote side physical layer. The method includes initiating an operational state of high-speed SerDes cable link interface, identifying flow-control packet Op codes not cited for use by operational high-speed SerDes cable link interface, transmitting a flow control signal from the local side physical layer to the remote side physical layer to control the remote side physical layer to monitor the eye characteristics of the channels used by the local side physical layer to transfer data to the remote side physical layer, transferring eye characteristics acquired in the monitoring to the local side physical layer and processing the eye characteristics by the local side physical layer to generate equalization setting adjustments.

Abstract: A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.

Abstract: A multiport valve is taught for regulating flow of liquid therethrough originating from at least two sources. The valve includes a three cylindrical valve chambers each having a piston residing therein such that through actuation of the pistons flow through each valve chamber can be permitted or stopped independently. There is an inlet port that tangentially intercepts the first cylindrical valve chamber and there is an outlet port that tangentially intercepts an intermediate cylindrical valve chamber. The design of the three valve chambers and the inlet and outlet ports to the valve chambers effectively eliminates any bubble traps in the valve and allows bubbles to be swept from the valve chambers.

Abstract: A method and apparatus for switching a supply to a process from a first vessel to a second vessel. Liquid is flowed from the first vessel through a first outlet conduit through a vessel selection valve, including first and second switch valves, to the process. A conductivity sensor measures the conductivity level of the liquid in the first outlet conduit at a point upstream of the selection valve and a computer compares the conductivity level to a predetermined range. The computer signals an isolation valve, in a second outlet conduit from the second vessel, to open and allow liquid to displace air in the second outlet conduit from the second vessel to the selection valve. The computer determines a delay to allow liquid below the first conductivity sensor to reach the first switch valve, then closes the first switch valve and opens the second switch valve.