Abstract: A method and apparatus is taught for switching supply to a downstream process from a first vessel containing a first batch of a liquid composition to a second vessel containing a second batch of the liquid composition. The liquid is flowed from the first vessel through a first outlet conduit from the first vessel and through a vessel selection valve to the downstream process, the vessel selection valve including a first switch valve and a second switch valve. A conductivity sensor measures the conductivity level of the liquid composition at a point in the outlet conduit from the first vessel before the vessel selection valve and a computer compares the conductivity level to a predetermined range. The computer signals a vessel isolation valve in the second outlet conduit from the second vessel to open thereby displacing air in the second outlet conduit and filling the second outlet conduit with the liquid composition from the second vessel to the vessel selection valve.

Abstract: A multiport valve is taught for regulating flow of liquid therethrough originating from at least two sources. The valve includes a three cylindrical valve chambers each having a piston residing therein such that through actuation of the pistons flow through each valve chamber can be permitted or stopped independently. There is an inlet port that tangentially intercepts the first cylindrical valve chamber and there is an outlet port that tangentially intercepts an intermediate cylindrical valve chamber. The design of the three valve chambers and the inlet and outlet ports to the valve chambers effectively eliminates any bubble traps in the valve and allows bubbles to be swept from the valve chambers.

Abstract: A method for switching filters on-line while continuously supplying a fluid to a downstream operation such as a photographic product coating device comprising transmitting the fluid to a filter selection valve having a first flow path therethrough to a first filter and a second flow path therethrough to a second filter; flowing the fluid through the first flow path and through the first filter to a filter diverter valve having a first fluid from the first filter to the downstream operation, a second fluid path from the second filter to the downstream operation, a third fluid path from the first filter to a drain, and a fourth fluid path from the second filter to the drain; directing the fluid through the first fluid path; determining when the first filter will soon become inoperable; opening the second flow path through the filter selection valve and opening the fourth fluid path through the filter diverter valve; closing the fourth fluid path after the fluid has flowed through the second filter but prior to

Abstract: A Synchronous DRAM memory test assembly that converts a normal PC or Workstation with a synchronous bus into a memory tester. The test assembly may be split into two segments: a diagnostic card and an adapter card to limit mechanical load on the system socket as well as permit varying form factors. This test assembly architecture supports memory bus speeds of 66 MHz and above, and provides easy access for a logic analyzer. The test assembly supports Registered and Unbuffered Synchronous DRAM products. The test assembly permits good and questionable synchronous modules to be compared using an external logic analyzer. It permits resolution of in-system fails that occur uniquely in system environments and may be otherwise difficult or impossible to replicate.

Abstract: A system for integrating data among heterogeneous source applications and destination applications including a knowledge repository containing temporary data storage for storing data from the source applications during processing for population in the destination applications, a library of data elements each providing a discrete data manipulation friction, configuration data storage for storing user-provided information describing the integration environment, and a plurality of add-on modules or cartridges which each include a plurality of predefined instruction sets defining chains of data elements to perform interface functions corresponding to a particular destination application. The underlying interface communication and processing functions are performed by an active component (or engine) according to the configuration data and the module instruction sets.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. First the single or dual in-line memory module (SIMM or DIMM) includes in-line bus switches. The bus switches are between the SIMM or DIMM module tabs (system) and random access memory devices (RAM) and are either in a high impedance (off) or active state depending on the READ/WRITE state of the RAM. When in the high impedance state, the effective loading of the module is that of the bit switch device. The logic for determining the READ/WRITE state may be embedded in an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches, be provided by a memory controller or, generated by the RAM itself. The bus switches are active when the RAM is performing a read or a write and inactive otherwise.

Abstract: A PCMCIA card comprises a plurality of I/O functions. Each has an interrupt signal, but the card has only one interrupt request (IREQ) line. The card is provided with an interrupt status register (ISR) to receive the interrupt signals from each of the I/O functions. This ISR allows software to determine the function that signaled the interrupt. The card is also provided with interrupt control logic (ICL) that is responsive to the interrupt status of ISR. The ICL sends an IREQ signal to a host system.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches.

Abstract: A method and logic circuit are provided which method and logic circuit allow both a CBR and hidden refresh to take place on DRAM's populating SIMM's or DIMM's, wherein both a single system RAS and single system CAS are converted to multiple RAS's and multiple CAS's for normal read/write operation on the DRAM's.