Abstract: Systems and methods for mapping an iterative time-based data acquisition (DAQ) operation to an isochronous data transfer channel of a network. A time-sensitive buffer (TSB) associated with the isochronous data transfer channel of the network may be configured. A data rate clock may and a local buffer may be configured. A functional unit may be configured to initiate continuous performance of the iterative time-based DAQ operation, transfer data to the local buffer, initiate transfer of the data between the local buffer and the TSB at a configured start time, and repeat the transferring and initiating transfer in an iterative manner, thereby transferring data between the local buffer and the TSB. The TSB may be configured to communicate data over the isochronous data transfer channel of the network, thereby mapping the iterative time-based DAQ operation to the isochronous data transfer channel of the network.

Abstract: System and methods for synchronizing real time networks. Systems may include a first device located on a first real time network that may include a functional unit, a port, and a plurality of output queues configured for segregation of network packets based on a mapping of one or more additional real time networks to respective output queues. For each of the one or more additional real time networks, synchronization packets may be generated based on a master clock. The packets may be usable by a network timekeeper of the additional real time network to synchronize the additional real time network to the master clock. The synchronization packets may be stored in a respective output queue based on the mapping and may be sent to the network timekeeper of the additional real time network via the port.

Abstract: Systems and methods for interoperating between real time networks. Systems may include a plurality of ports and switch circuitry coupled to the plurality of ports. At least one port may be coupled to a first real time network carrying first traffic. One or more other ports may be coupled to a second real time network carrying second traffic. Switch circuitry may route packets between the first real time network and the one or more second real time networks based on a mapping. Routing information may be inserted in packets routed from the one or more second real time networks to the first real time network and routing information may be removed from the packets routed from the first real time network to the one or more second real time networks. Packets may be routed based on the mapping to distinct queues for the first and second traffic.

Abstract: Systems and methods for scheduling data egress from a network switch. Systems may include switch circuitry, a plurality of ports, and a plurality of queues. Each port may be associated with a respective set of routing information for network packets and each port may be configured with a respective set of egress periods. Each network packet may have respective routing information and a type that specifies a respective egress period. Each queue may be associated with a respective network packet type and a port of the plurality of ports.

Abstract: Systems and methods for interoperating between a time-sensitive (TS) network and a non-time-sensitive (NTS) network. The system may include a TS network switch and a TS network interface controller (NIC). Each may have a functional unit. A first port of the TS switch may be coupled to an NTS node of the NTS network and its functional unit may be configured to manage insertion and removal of tags associating packets received from the NTS network with the NTS network. The tagged packets may be forwarded on to the TS NIC via a second port. The functional unit of the TS NIC may be configured to queue tagged packets received from the TS network switch and queue and tag packets destined for the NTS network via the TS network switch.

Abstract: Systems and methods for synchronizing clocks across networks using a time-sensitive (TS) network interface controller (NIC). The TS NIC may include a functional unit, a port, a clock, a plurality of input/output queue pairs, and a time stamp unit (TSU). The functional unit may be configured to generate synchronization packets usable by an NTS network timekeeper of a respective NTS network to synchronize the NTS network to the master clock, including using the TSU to generate time stamps for the synchronization packets in accordance with the clock synchronized to the master clock and communicate with the respective NTS network via the port using the corresponding input/output queue pair, including sending the synchronization packets to the NTS network timekeeper of the respective NTS network.

Abstract: Systems and methods for scheduling data egress using a time-sensitive (TS) network switch. The TS network switch may include a functional unit, a plurality of ports, and a plurality of queues. Each port may be associated with a set of network addresses for TS packets and may be configured with a set of egress periods. Each queue may be associated with a TS packet type and a port. The functional unit may be configured to receive TS packets asynchronously from a network node via a first port, determine a second port for egressing a TS packet, determine an egress period for egressing the TS packet, determine that the TS packet cannot currently be egressed from the second port, queue the TS packet in a first queue, where the first queue is associated with the second port, and egress the TS packet in the respective time window from the second port.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

Abstract: System and method for debugging a graphical program deployed to hardware. The graphical program may be received. The graphical program may include a plurality of nodes and connections between the nodes which visually represents functionality of the graphical program. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be deployed to the programmable hardware element and the programmable hardware element may be executed. The graphical program may be displayed on a display of a host computer system that is coupled to the programmable hardware element. Debugging information may be received from the programmable hardware element during the executing. The debugging information from the programmable hardware element may be displayed in the graphical program displayed on the display.

Abstract: Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple models of computation. A graphical program may be received which includes a first portion having a first computational model and a second portion having a second computational model. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to implement functionality of the graphical program.

Abstract: Generating a hardware description for a programmable hardware element based on a graphical program including multiple physical domains. A graphical program may be received which includes a first portion of a first physical domain for simulating a first portion of a physical system. The graphical program may include a second portion of a second physical domain for simulating a second portion of the physical system. A hardware description may be generated based on the graphical program. The hardware description may describe a hardware implementation of the graphical program. The hardware description may be configured to configure a programmable hardware element to simulate the physical system.

Abstract: Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Abstract: One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During operation, at least one of the counter units may receive a measurement signal (or input signal) acquired by the data acquisition device and also a sample clock signal. The counter unit may sample the measurement signal based on the selected operational mode and timing of the sample clock, and at a rate that is independent of the frequency of the measurement signal. Furthermore, the counter unit may sample the measurement signal based on a selected one of a plurality of timing modes associated with the sample clock signal. The counter units may take samples of the measurement signal to perform at least one of the following types of measurements: period, frequency, pulse-width, semi-period, time separation, or event counting.

Abstract: A counter module may include a first set of registers configured to store respective sets of first control data, a second set of registers configured to store respective sets of second control data, a first counter and a second counter. The first counter may be coupled to the first set of registers and may receive counter input signals and an internal control signal, and generate a first count output and a first terminal count output according to one of the respective sets of the first control data, the internal control signal, and the counter input signals. The second counter may be coupled to the first counter and to the second set of registers, and may receive the counter input signals, generate the internal control signal, and generate a second count output and a second terminal count output according to one of the respective sets of the second control data and the counter input signals.

Abstract: A counter module may include a first set of registers configured to store respective sets of first control data, a second set of registers configured to store respective sets of second control data, a first counter and a second counter. The first counter may be coupled to the first set of registers and may receive counter input signals and an internal control signal, and generate a first count output and a first terminal count output according to one of the respective sets of the first control data, the internal control signal, and the counter input signals. The second counter may be coupled to the first counter and to the second set of registers, and may receive the counter input signals, generate the internal control signal, and generate a second count output and a second terminal count output according to one of the respective sets of the second control data and the counter input signals.

Abstract: Provided in some embodiment is a computer system, including a first peripheral device, having a first external data input, a first peripheral storage device to store the measurement data, a first peripheral device output to couple to a system interconnect of the computer system. The first peripheral device capable of receiving measurement data via the external data input the first peripheral device capable of transferring at least a portion of the measurement data to a second peripheral device of the computer system via the system interconnect, and where the second peripheral device is capable of processing at least a portion of the measurement data transferred to the second peripheral device.

Abstract: Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device.

Abstract: System and method for measurement, DAQ, and control operations which uses small form-factor measurement modules or cartridges with a re-configurable carrier unit, sensors, and a computer system to provide modular, efficient, cost-effective measurement solutions. The measurement module includes measurement circuitry, e.g., signal conditioner and/or signal conversion circuitry, and interface circuitry for communicating with the carrier unit. The module communicates interface information to the carrier unit, which informs the computer system how to program or configure a functional unit on the carrier unit to implement the communicated interface, or sends the information directly to the computer system. The computer system programs the carrier unit with the interface, and the programmed carrier unit and measurement module together function as a DAQ, measurement, and/or control device.