Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program.

Abstract: A method for operating a system that includes several subsystems may involve establishing one or more synchronized timelines for the system; allocating timeslots within each of the timelines for operation of one or more devices in the system; detecting an input event asynchronously to the timeline; generating a timestamp indicative of the time at which the input event is detected relative to the timeline; performing a processing task in response to the input event during a time slot allocated to the processing task; and inhibiting generation of an output event until a second time relative to the timelines. Performing the processing task may generate data representative of the output event as well as data representative of the second time. The second time may be a pre-determined time interval after the input event detection time.

Abstract: Various embodiments of a system and method for configuring a set of DMA resources as multiple virtual DMA channels are disclosed. In one embodiment, a system may include a context memory configured to store context parameters for each of the virtual DMA channels, a set of DMA resources, a DMA controller coupled to the context memory, and several I/O resources. The DMA controller is configured to configure the set of DMA resources as different virtual DMA channels using context parameters associated with different respective ones of the virtual DMA channels. Each virtual DMA channel corresponds to one of the I/O resources.

Abstract: A system and method for generating a graphical program based on a timing diagram created or specified by the user. The user may first draw a timing diagram on the display of a device that specifies timing relationship(s) among two or more signals. As a result, data structure(s) may be stored in memory which comprise information represented by the timing diagram. A graphical program may then be programmatically generated based on the timing diagram. For example, a graphical program generation (GPG) software program executing on the computer system may execute to analyze the timing diagram (e.g., analyze the stored data structure(s) that represent the timing diagram) and programmatically generate a graphical program that corresponds to the timing diagram. The generated graphical program may be configured to execute according to the timing diagram as drawn by the user.

Abstract: An instrumentation system may include a base card that is configurable to perform multiple instrumentation tasks. The base card includes a programmable logic device (PLD) that is configured according to a hardware description. One of a plurality of possible daughter cards, e.g., a first daughter card or a second daughter card, may be coupled to the base card. One or more of: 1) providing a selected hardware description to the PLD; or 2) coupling of a selected daughter card to the base card may configure the reconfigurable instrumentation card to perform a desired instrumentation function. Thus, by selecting which of the daughter cards is coupled to the base card and/or by selecting which hardware description is used to configure the PLD, the base card may be reconfigured to perform different sets of instrumentation tasks.

Abstract: A system and method for debugging a program which is intended to execute on a reconfigurable device. A computer system stores a program that specifies a function, and which is convertible into a hardware configuration program (HCP) and deployable onto a programmable hardware element comprised on the device. The HCP is generated based on the program, specifies a configuration for the programmable hardware element that implements the function, and further specifies usage of one or more fixed hardware resources by the programmable hardware element in performing the function. A test configuration is deployable on the programmable hardware element by a deployment program, where, after deployment, the programmable hardware element provides for communication between the fixed hardware resources and the program. The program is executable by a processor in the computer system, where during execution the program communicates with the one or more fixed hardware resources through the programmable hardware element.

Abstract: A system and method for configuring a device to perform a function, where the device includes a programmable hardware element and one or more fixed hardware resources. A program is stored which represents the function. A hardware configuration program is generated based on the program, specifying a configuration for the programmable hardware element that implements the function, and usage of the fixed hardware resources by the programmable hardware element in performing the function. A deployment program deploys the hardware configuration program onto the programmable hardware element, where, after deployment, the device is operable to perform the function, where the programmable hardware element directly performs a first portion of the function, and the programmable hardware element invokes the fixed hardware resources to perform a second portion of the function. An optional measurement module couples to the device and performs signal conditioning and/or conversion logic on an acquired signal for the device.

Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may optionally be compiled into machine code for execution by a CPU, and another portion of the graphical program may be converted into a hardware implementation on a programmable hardware element. The programmable hardware element is configured utilizing a hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may optionally be compiled into machine code for execution by a CPU, and another portion of the graphical program may be converted into a hardware implementation on a programmable hardware element. The programmable hardware element is configured utilizing a hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.

Abstract: A system for generating waveforms may include a memory configured to store a plurality of waveform segments, a plurality of waveform segment queues each coupled to receive waveform segments output by the memory, and a selection unit coupled to each of the waveform segment queues and configured to read waveform segments out of a selected one of the waveform segment queues. Each of the waveform segment queues may be configured to store a series of one or more waveform segments. The selection unit may be configured to access the first waveform segment queue during a first time period and to access the second waveform segment queue if a first trigger occurs.

Abstract: System and method for measurement, DAQ, and control operations. A measurement module includes measurement circuitry for performing signal conditioning and/or signal conversion, and interface circuitry which provides an interface for the measurement circuitry. A carrier unit couples to the interface circuitry of the module. A computer system couples to the carrier unit and stores one or more hardware configuration programs. The interface circuitry communicates an interface protocol describing the interface, e.g., to the carrier unit or the computer system. The computer system provides a hardware configuration program in response to the communicated interface protocol, and programs one or more programmable hardware elements on the carrier unit with the hardware configuration program. After being configured, the programmable hardware elements interface with the measurement module in accordance with the communicated interface protocol.

Abstract: A computer-implemented system and method for generating a hardware implementation of graphical code. The method may operate to configure an instrument to perform measurement functions, wherein the instrument includes a programmable hardware element. The method comprises first creating a graphical program, wherein the graphical program may implement a measurement function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program.

Abstract: A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware—i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium—and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary.

Abstract: A computer-implemented system and method for deploying a graphical program onto an image acquisition (IMAQ) device. The method may operate to configure an image acquisition (IMAQ) device to perform image processing or machine vision functions, wherein the device includes a programmable hardware element and/or a processor and memory. The method comprises first creating a graphical program which implements the image processing or machine vision function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program. The CPU-executable code may be executed by a computer coupled to the IMAQ device, or by a processor/memory on the IMAQ device.

Abstract: A VXI device which intelligently monitors transactions on the VXI bus and begins early cycles on the bus where possible, thereby improving system performance. The VXI 0device includes a VXI bus master device and a VME bus requester. When the bus master desires the bus, the VXI bus master issues a Device Wants Bus signal to its VME requester directing the requester to gain control of the VXI bus for the device or master. The VME requester then attempts to gain control of the bus for the bus master. According to the present invention, the VME requester also monitors the VXI bus and generates the bus release signal to the master to inform the master whether it is about to lose the bus. The bus release signal provides an indication to the bus master whether the bus master can begin early cycles on the bus. Therefore, the present invention provides improved performance of VXI controllers and devices coupled to the VXI bus.

Abstract: A system and method for performing more efficient hardware context switches in a computer-controlled instrumentation system including a computer system which controls a plurality of instruments. The instrumentation system includes a direct memory access transfer device which performs various data transfers between the computer system and the various instruments. The system also includes a plurality of processes executing in the computer system which operates through a common window to map cycles onto the instrumentation bus to the various instruments. Each process or thread executing on the CPU requires a specific context, and the DMA transfer device automatically configures itself to different contexts in parallel with operating system context changes. Each process includes corresponding context information stored in memory. When the operating system is invoked to switch in a new process on the CPU, the operating system writes the address of the context information to the DMA transfer device.

Abstract: An instrumentation system according to the present invention which automatically demultiplexes multiplexed data received from multiple analog channels. The system includes a plurality N of analog channels that are multiplexed into an A/D converter. The A/D converter in turn supplies the multiplexed or interleaved digital data to an external computer where the data is stored in memory. The external computer includes direct memory access (DMA) demultiplexing logic according to the present invention which automatically reads the multiplexed data and rewrites the multiplexed data into a non-interleaved or demultiplexed format. Once all the multiplexed digital data has been received and stored in the computer system, the demultiplexing logic of the present invention performs DMA transfers to demultiplex or de-interleave the data into N independent buffers or memory spaces which are no longer interleaved.

Abstract: A system and method for rapidly transferring large amounts of small-sized data to non-sequential addresses in an instumentation system. According to a preferred embodiment, a host computer includes a plurality of test vectors stored in memory which control the operation of attached instruments. The host processor generates a block of address/data pairs in response to the test vectors, with each pair containing data and a destination address. This block is stored in memory and the address of the block is provided to a random write engine. The random write engine then distributes the data to the respective instruments at the proper addresses with minimal processor invention. Therefore, large amounts of small-sized data may be rapidly transferred to non-sequential addresses without burdening the processor.

Abstract: A system and method for performing more efficient hardware context switches in a computer-controlled instrumentation system including a computer system which controls a plurality of instruments. The instrumentation system includes a direct memory access transfer device which performs various data transfers between the computer system and the various instruments. The direct memory access transfer device includes different hardware contexts for different transfers, and the DMA transfer device automatically configures itself to different contexts with minimal CPU involvement. For each process or thread requiring a different DMA transfer device context, the CPU prepares the context information and stores the context in memory. The CPU then provides a request list to the DMA transfer device including interleaved context pointers and data transfer packets.