Patents by Inventor Brian M. Henderson
Brian M. Henderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9184130Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.Type: GrantFiled: October 5, 2012Date of Patent: November 10, 2015Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Chiew-Guan Tan, Gregory A. Uvieghara, Reza Jalilizeinali
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Patent number: 9153461Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.Type: GrantFiled: December 19, 2014Date of Patent: October 6, 2015Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Shiqun Gu
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Patent number: 9093462Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.Type: GrantFiled: May 6, 2013Date of Patent: July 28, 2015Assignee: QUALCOMM IncorporatedInventors: Vidhya Ramachandran, Brian M. Henderson, Shiqun Gu, Chiew-Guan Tan, Jung Pill Kim, Taehyun Kim
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Patent number: 9041220Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.Type: GrantFiled: February 13, 2013Date of Patent: May 26, 2015Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Shiqun Gu
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Publication number: 20150102509Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.Type: ApplicationFiled: December 19, 2014Publication date: April 16, 2015Inventors: Brian M. HENDERSON, Shiqun GU
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Publication number: 20140327105Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.Type: ApplicationFiled: May 6, 2013Publication date: November 6, 2014Applicant: QUALCOMM IncorporatedInventors: Vidhya Ramachandran, Brian M. Henderson, Shiqun Gu, Chiew-Guan Tan, Jung Pill Kim, Taehyun Kim
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Publication number: 20140225280Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: Qualcomm IncorporatedInventors: Brian M. Henderson, Shiqun Gu
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Publication number: 20140225248Abstract: Some implementations provide an apparatus that includes a package substrate, a first die coupled to the package substrate, and a second die coupled to the first die. The die package also includes a heat spreader coupled to the second die, the heat spreader configured to (i) dissipate heat from the second die, and (ii) provide an electrical path for a power signal to the second die. In some implementations, the die package also includes a molding surrounding the first die and the second die. The die package also includes several through mold vias (TMVs) coupled to the heat spreader. The TMVs are configured to provide an electrical path for the power signal to the second die through the heat spreader. In some implementations, the TMVs traverse the molding.Type: ApplicationFiled: March 1, 2013Publication date: August 14, 2014Applicant: QUALCOMM IncorporatedInventors: Brian M. Henderson, Shiqun Gu
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Publication number: 20140098448Abstract: One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.Type: ApplicationFiled: October 5, 2012Publication date: April 10, 2014Applicant: QUALCOMM IncorporatedInventors: Brian M. Henderson, Chiew-Guan Tan, Gregory A. Uvieghara, Reza Jalilizeinali
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Patent number: 8604626Abstract: Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.Type: GrantFiled: May 14, 2012Date of Patent: December 10, 2013Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Ronnie A. Lindley, Dong Wook Kim, Reza Jalilizeinali, Shiqun Gu, Matthew M. Nowak
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Patent number: 8557680Abstract: A process for wafer-to-wafer bonding of a first wafer having a first set of dies of a first die size to a reconstituted wafer of a second set of dies having a second die size different than the first die size. The process includes aligning the second set of dies such that a second set of interconnects on the second set of dies aligns with a first set of interconnects on the first set of dies. The second set of dies includes a spacing between the second set of dies based on parameters of the first set of dies. The process also includes coupling the reconstituted wafer with the first wafer to create a wafer stack.Type: GrantFiled: July 10, 2012Date of Patent: October 15, 2013Assignee: QUALCOMM IncorporatedInventors: Arvind Chandrasekaran, Brian M. Henderson
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Publication number: 20130127046Abstract: Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.Type: ApplicationFiled: May 14, 2012Publication date: May 23, 2013Applicant: QUALCOMM INCORPORATEDInventors: Brian M. Henderson, Ronnie A. Lindley, Dong Wook Kim, Reza Jalilizeinali, Shiqun Gu, Matthiew M. Nowak
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Patent number: 8362599Abstract: Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.Type: GrantFiled: September 24, 2009Date of Patent: January 29, 2013Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Brian M. Henderson, Matthew M. Nowak, Jiayu Xu
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Patent number: 8319325Abstract: A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a redistribution layer with a first electrical terminal coupled to the plurality of circuit components by a first through-silicon via, and a second through-silicon via electrically coupled to a third through-silicon via by a trace on the back side redistribution layer. Also, disclosed is a method of coupling circuit components on a die using through-silicon vias and a back side redistribution layer.Type: GrantFiled: June 12, 2009Date of Patent: November 27, 2012Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Chandra Sekhar Nimmagadda
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Publication number: 20120276716Abstract: A process for wafer-to-wafer bonding of a first wafer having a first set of dies of a first die size to a reconstituted wafer of a second set of dies having a second die size different than the first die size. The process includes aligning the second set of dies such that a second set of interconnects on the second set of dies aligns with a first set of interconnects on the first set of dies. The second set of dies includes a spacing between the second set of dies based on parameters of the first set of dies. The process also includes coupling the reconstituted wafer with the first wafer to create a wafer stack.Type: ApplicationFiled: July 10, 2012Publication date: November 1, 2012Applicant: QULCOMM IncorporatedInventors: Arvind Chandrasekaran, Brian M. Henderson
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Patent number: 8242543Abstract: A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes.Type: GrantFiled: August 26, 2009Date of Patent: August 14, 2012Assignee: QUALCOMM IncorporatedInventors: Arvind Chandrasekaran, Brian M. Henderson
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Patent number: 8198736Abstract: A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.Type: GrantFiled: April 9, 2009Date of Patent: June 12, 2012Assignee: QUALCOMM IncorporatedInventors: Brian M. Henderson, Reza Jalilizeinali, Shiqun Gu
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Publication number: 20110068433Abstract: Method of forming a radio frequency integrated circuit (RFIC) is provided. The RFIC comprises one or more electronic devices formed in a semiconductor substrate and one or more passive devices on a dielectric substrate, arranged in a stacking manner. Electrical shield structure is formed in between to shield electronic devices in the semiconductor substrate from the passive devices in the dielectric substrate. Vertical through-silicon-vias (TSVs) are formed to provide electrical connections between the passive devices in the dielectric substrate and the electronic devices in the semiconductor substrate.Type: ApplicationFiled: September 24, 2009Publication date: March 24, 2011Applicant: QUALCOMM IncorporatedInventors: Jonghae Kim, Brian M. Henderson, Matthew M. Nowak, Jiayu Xu
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Publication number: 20110049694Abstract: A semiconductor manufacturing process for wafer-to-wafer stacking of a reconstituted wafer with a second wafer creates a stacked (3D) IC. The reconstituted wafer includes dies, die interconnects and mold compound. When stacked, the die interconnects of the reconstituted wafer correspond to die interconnects on the second wafer. Wafer-to-wafer stacking improves throughput of the manufacturing process. The reconstituted wafer may include dies of different sizes than those in the second wafer. Also, the dies of the reconstituted wafer may be singulated from a wafer having a different size than the second wafer. Thus, this wafer-to-wafer manufacturing process may combine dies and/or wafers of dissimilar sizes.Type: ApplicationFiled: August 26, 2009Publication date: March 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Arvind Chandrasekaran, Brian M. Henderson
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Publication number: 20100314737Abstract: A semiconductor die includes: a body portion with a plurality of circuit components, a front side including electrical couplings to the plurality of circuit components, a back side having a redistribution layer with a first electrical terminal coupled to the plurality of circuit components by a first through-silicon via, and a second through-silicon via electrically coupled to a third through-silicon via by a trace on the back side redistribution layer. Also, disclosed is a method of coupling circuit components on a die using through-silicon vias and a back side redistribution layer.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: QUALCOMM INCORPORATEDInventors: Brian M. Henderson, Chandra Sekhar Nimmagadda