Abstract: A method to reduce electrostatic discharge susceptibility when assembling a stacked IC device. The method includes coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus minimizing potential damage to sensitive circuit elements.

Abstract: An integrated circuit for measuring conductor misalignment comprises: a set of 2n+1 conductor pairs where n is a predetermined positive integer; each conductor pair includes a U-shaped conductor having a central axis; each conductor pair also includes a rectangular shaped conductor having a central axis and which is narrow enough to fit between the legs of the U-shaped conductor provided their central axis are aligned; and the rectangular shaped conductor of each conductor pair has its central axis a distance .delta.+k.DELTA.d from the central axis of the U-shaped conductor where .DELTA.d is a fixed increment, k is an integer between +n and -n that differs for each conductor pair, and .delta.is a misalignment between the central axis of each conductor pair.