Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: A method for allowing in-place programming of clock buffer delays of clock buffers in an integrated circuit clock tree is presented. The clock tree comprises at least one clock driver connected between a clock driver input line and a clock driver output line. Each clock driver comprises a plurality of clock buffers connected in series between the clock driver input line and, potentially, the clock driver output line. Metal is reserved in intervening metal layers within a clock driver block between the clock driver input line and the input of a first one of said plurality of clock buffers in the variable clock buffer chain. Metal is reserved on one or more metal layers for connecting the output of each of the clock buffers in the clock buffer chain to the clock driver output line. The metal layers are partitioned into one or more programming layers and one or more non-programming layers.

Abstract: A high-precision high-linearity digital-to-analog converter (DAC) and a method for converting a digital input signal having N bits to a substantially equivalent analog current output signal is presented. The DAC segments the digital input signal bits into groups separate processing. The invention includes a first current-steering digital-to-analog converter configured to receive a first group of i input signal bits and a first reference current to produce a first current signal. A second current-steering digital-to-analog converter is configured to receive a second group of j input signal bits and the first reference current to produce an intermediate current signal. The intermediate current signal is scaled down by a factor of 2j to produce a second current signal. A summing circuit sums at least the first and second current signals to produce an analog current signal representative of the digital input signal value.

Abstract: Systems, methods, and computer program products for relating a hyper-text markup language (HTML) document to stored information associated with the HTML document and with an application program are provided for by an association module that searches the HTML document for an association tag, wherein the association tag includes an index reference to a location of the stored information. Upon locating an association tag, the index reference is read and utilized by the association module to locate and retrieve the stored information. The stored information is then utilized by the application program. The association tag may also include a marker that uniquely identifies it as associated with the application program. In accordance with an aspect of the present invention, the stored information is both document and application specific.

Abstract: A method for accurately analyzing the timing of a clock network on a piecemeal basis in an integrated circuit clock tree is presented. In accordance with the invention, the time delay of each individual subcircuit between an identified clock network node and an identified receiving endpoint may be individually determined. Tags are associated with the connection points of a child block and its parent block. A connection tool uses the tags to match up the connection points of the parent block to the respective connection points in the child block to allow a simulation tool to include the clock signal timing data of the child block in simulating the clock performance of the parent block.

Abstract: An electrochemical deposition apparatus and method for depositing a material onto a surface of a workpiece and for polishing the material are disclosed. The apparatus includes a platen and a polishing surface, including a conductive material and conductors embedded therein, disposed proximate the platen. During material deposition, a bias is applied across the conductor and the platen to cause deposition of material onto the workpiece surface.

Abstract: An electrochemical deposition apparatus and method for depositing a material onto a surface of a workpiece and for polishing the material are disclosed. The apparatus includes a platen and a polishing surface, including a conductive material and conductors embedded therein, disposed proximate the platen. During material deposition, a bias is applied across the conductor and the platen to cause deposition of material onto the workpiece surface.

Abstract: A process for removing a metallized surface from a workpiece is provided. A kinetic removal mechanism for removal of the metallized surface is characterized by a formation step for formation of a removable surface film and an abrasive step for removal of the film. The process includes causing the workpiece to contact a polishing surface while effecting relative motion between the workpiece and the polishing surface. The process also includes causing a polishing solution having less than 1 wt % of a polishing abrasive to be distributed at a contact area between the workpiece and the polishing surface so that the abrasive step is a rate-determining step of the removal mechanism.

Abstract: A pseudo language system and method are disclosed that permit an operator to meaningfully test multibyte character data in an application such as a software application. The operator can enter single byte characters through an input device. The pseudo language keyboard utility then transcribes the single byte characters into multibyte characters of a pseudo language. The pseudo language characters are entered into the application under test and may be displayed and/or printed. The multibyte pseudo language characters are preferably constructed to appear visually recognizable to the native language of the operator. In this manner, the operator can determine whether the testing has been successful or not as is especially desirable for initial application testing.

Abstract: A system for accessing data. The system includes a memory mechanism having the data. The system includes a mechanism for processing a query for the memory mechanism which is icon based. A system for accessing data. The system includes a memory mechanism having N heterogeneous memory sections having the data. The system includes a mechanism for processing queries for at least two of the N memory sections. A system for accessing data. The system includes a mechanism for processing queries along respective query paths for the memory mechanism. The processing mechanism has predefined query paths to process queries. A method for accessing data. A system for accessing data. The system includes a design time processing portion and a run time processing portion. A system for accessing data. The system includes a memory mechanism having N memory sections having the data. The system includes a mechanism for processing a query which simultaneously obtains data from the N memory sections. A system for accessing data.

Abstract: Recovering text from a damaged electronic file by scanning an arbitrary stream of bytes and extracting text that is encoded as ASCII or Unicode. A byte of the damaged file is read. The read byte may be interpreted using the ASCII encoding standard. The read byte and the immediately preceding read byte may also be interpreted using the Unicode character encoding standard. The interpreted byte(s) is classified based upon the likelihood that the byte(s) is actually text for the particular character set rather than a control character, damaged data, or an element other than a textual character. The classifications are used to adjust a likelihood counter for each character type. The likelihood counter may be an integer value that indicates the probability that a text run has been detected. A text run is a sequence of bytes that is believed to be undamaged text. Each likelihood counter is then examined to determine whether there is a text run for one of the character types.