Abstract: An enhanced transistor gate drive is disclosed in which a pair of Kelvin sense leads measure the voltage potential across at the gate and source of the transistor. The difference in the voltage potential of the Kelvin sense lead from the gate and the Kelvin sense lead of the source is provided to a voltage controlled current source, which compares the output of the voltage differentiator to an oscillating voltage input. Changes to the voltage difference between the Kelvin sense connectors will result in more or less voltage being applied at the gate of the transistor, thereby parasitic inductance in the transistor from causing the device to switch on and off.

Abstract: A technique for addressing a low line voltage condition in an information handling system includes determining whether a magnitude of an input voltage of a power supply unit (PSU) is below a first threshold for at least a first time period. The technique also includes adjusting, based on the determining, a magnitude of a reference voltage of the PSU to track a magnitude of an output voltage of the PSU when the input voltage is below the first threshold for at least the first time period.

Abstract: A cost optimized redundant power supply consists of a plurality of power units (PUs) wherein each PU has two AC front ends. Each of the two AC front ends receive power from separate AC power sources, and each produce an isolated DC output. The isolated DC outputs from the two AC front ends are coupled to an input of one DC back end, e.g., DC-to-DC converter. Optimally, each of the AC front ends may have a power capacity of TRP/(N+1) and the DC back end may have a power capacity of TRP/N, where TRP=Total Redundant Power or the maximum system power required for operation and N is the number of PUs of the power supply.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: An information handling system has a power supply using a DC-to-DC buck converter. The DC-to-DC buck converter maintains continuous mode of operation over a wide range of output currents by adding more inductance to the buck converter circuit when the load current is below a certain value(s). A sensing circuit may determine load current and at the certain value(s) more inductance (increased inductance value) may be added to the buck converter circuit so as to main a continuous mode of operation. When the load current increases above the certain value, the extra inductance may be removed (inductance value decreased). Thus, the buck converter may operate most efficiently and remain in the continuous operation mode for a wider range of load currents.

Abstract: A technique for addressing a low line voltage condition in an information handling system includes determining whether a magnitude of an input voltage of a power supply unit (PSU) is below a first threshold for at least a first time period. The technique also includes adjusting, based on the determining, a magnitude of a reference voltage of the PSU to track a magnitude of an output voltage of the PSU when the input voltage is below the first threshold for at least the first time period.

Abstract: An alternating current (AC) to direct current (DC) power converter comprises a first electrical path in a primary circuit having an inductor coupled in series with a first primary winding and a first switch to a ground connection. A second electrical path in the primary circuit has the inductor coupled in series with a second primary winding and a second switch to the ground connection. A secondary circuit is electromagnetically coupled to the primary circuit. A controller operates the first switch and the second switch in a predetermined manner to induce a current in the secondary circuits.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: An addressing scheme to allow for a flexible DRAM configuration.

Abstract: An apparatus and method capable of verifying a scanned image utilizing a verification algorithm based on a topological analysis of the scanned image and an apparatus and method capable of verifying a scanned image utilizing a verification algorithm based on an improved bi-level separation analysis incorporating an anti-stroke scoring method with a character outlining method.

Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.

Abstract: The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.