Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.

Abstract: A method for synchronizing devices in a vehicle may make use of the Controller Area Network (CAN) communication bus. A bus interface of each of two or more devices coupled to the bus may be configured to accept a same message broadcast via the communication bus, in which the message has a specific message identification (ID) header. A message may be received from the communication bus that has the specific message ID simultaneously by each of the two or more devices. Operation of the two or more devices may be synchronized by triggering a task on each of the two or more devices in response to receiving the message having the specific message ID.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: A cascaded radar system is provided that includes a master radar system-on-a-chip (SOC) with transmission signal generation circuitry and a slave radar SOC coupled to an output of the master radar SOC to receive a signal from the transmission signal generation circuitry of the master SOC. In this system, the slave radar SOC is operable to measure phase noise in the signal received from the transmission signal generation circuitry of the master SOC.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: An integrated circuit (IC) is provided with a plurality of diode based mm-wave peak voltage detectors (PVD)s. During a testing phase, a multi-point low frequency calibration test is performed on one or more of the PVDs to determine and store a set of alternating current (AC) coefficients. During operation of the IC, a current-voltage sweep is performed on a selected one of the PVDs to determine a process and temperature direct current (DC) coefficient. A peak voltage produced by the PVD in response to a high frequency radio frequency (RF) signal is measured to produce a first measured voltage. An approximate power of the RF signal is calculated by adjusting the first measured voltage using the DC coefficient and the AC coefficient.

Abstract: A radar system is provided that includes a first radar transceiver integrated circuit (IC) including transmission signal generation circuitry operable to generate a continuous wave signal and a first transmit channel coupled to the transmission generation circuitry to receive the continuous wave signal and transmit a test signal based on the continuous wave signal, and a second radar transceiver IC including a first receive channel coupled to an output of the first transmit channel of the first radar transceiver IC via a loopback path to receive the test signal from first the transmit channel, the second radar transceiver IC operable to measure phase response in the test signal.

Abstract: A radar device is provided that includes a timing control component operable to generate, for each chirp of a sequence of chirps according to a set of chirp configuration parameters and a chirp profile for the chirp, chirp control signals to cause the radar device to transmit the chirp, the timing control component having chirp configuration parameter inputs, chirp profile parameter inputs, a chirp address output, and chirp control signal outputs, a chirp configuration storage component having chirp configuration parameter outputs coupled to corresponding inputs of the configuration parameter inputs of the timing control component, a chirp profile address output, and a chirp address input coupled to the chirp address output, and a chirp profile storage component having chirp profile parameter outputs coupled to the chirp profile parameter inputs of the timing control component; and a chirp profile address input coupled to the chirp profile address output.

Abstract: A system having a set of power amplifiers each having a primary inductive structure configured to provide an output signal. A secondary inductive structure is configured to inductively couple to each of the primary inductive structures. A transmission line is provided with a signal trace and a ground trace. The signal trace of the transmission line is connected to a first end of the secondary inductive structure. A return path from a second end of the secondary inductive structure is coupled via a resonant network to the ground trace of the transmission line, in which the return path is spaced away from the secondary inductive structure to minimize inductive coupling to the primary structures.

Abstract: An integrated circuit (IC) is provided with a plurality of diode based mm-wave peak voltage detectors (PVD)s. During a testing phase, a multi-point low frequency calibration test is performed on one or more of the PVDs to determine and store a set of alternating current (AC) coefficients. During operation of the IC, a current-voltage sweep is performed on a selected one of the PVDs to determine a process and temperature direct current (DC) coefficient. A peak voltage produced by the PVD in response to a high frequency radio frequency (RF) signal is measured to produce a first measured voltage. An approximate power of the RF signal is calculated by adjusting the first measured voltage using the DC coefficient and the AC coefficient.

Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Abstract: A system having a set of power amplifiers each having a primary inductive structure configured to provide an output signal. A secondary inductive structure is configured to inductively couple to each of the primary inductive structures. A transmission line is provided with a signal trace and a ground trace. The signal trace of the transmission line is connected to a first end of the secondary inductive structure. A return path from a second end of the secondary inductive structure is coupled via a resonant network to the ground trace of the transmission line, in which the return path is spaced away from the secondary inductive structure to minimize inductive coupling to the primary structures.

Abstract: A frequency modulated continuous wave (FMCW) radar system is provided that includes a receiver configured to generate a digital intermediate frequency (IF) signal, and an interference monitoring component coupled to the receiver to receive the digital IF signal, in which the interference monitoring component is configured to monitor at least one sub-band in the digital IF signal for interference, in which the at least one sub-band does not include a radar signal.

Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: A cascaded radar system is provided that includes a first radar system-on-a-chip (SOC) operable to perform an initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels of the radar SOC, a second radar SOC operable to perform the initial portion of signal processing for object detection on digital beat signals generated by multiple receive channels in the radar SOC, and a processing unit coupled to the first radar SOC and the second radar SOC to receive results of the initial portion of signal processing from each radar SOC, the processing unit operable to perform a remaining portion of the signal processing for object detection using these results.

Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.

Abstract: A radar system is provided that includes a first radar transceiver integrated circuit (IC) including transmission signal generation circuitry operable to generate a continuous wave signal and a first transmit channel coupled to the transmission generation circuitry to receive the continuous wave signal and transmit a test signal based on the continuous wave signal, and a second radar transceiver IC including a first receive channel coupled to an output of the first transmit channel of the first radar transceiver IC via a loopback path to receive the test signal from first the transmit channel, the second radar transceiver IC operable to measure phase response in the test signal.