Abstract: One or more embodiments may include a method for selectively charging a vehicle. The method may include receiving at one or more computers one or more periods for charging a vehicle. The vehicle charging periods may be stored in memory. Further, pricing rates for charging the vehicle during the one or more vehicle charging periods may be received at the computer(s). Based on the one or more pricing rates and the vehicle charging periods, one or more low cost charging periods may be determined. The one or more low cost charging periods may be automatically adjusted if the one or more pricing rates change. The vehicle may be charged during at least part of the one or more low cost charging periods.

Abstract: One or more embodiments may include a method for remotely obtaining information about an energy source of a vehicle. Information identifying one or more vehicles and one or more drivers of the vehicles may be received at one or more computing devices remote from a vehicle. Instructions from the one or more remote computing devices may be transmitted requesting information from the identified vehicle(s) about a status of an energy source for the identified vehicle(s). The status information may be received at the remote computing device(s). Based on the energy source status information and the driver identifying information, a vehicle energy source status with respect to one or more attributes of the vehicle drivers may be calculated. Additionally, the vehicle energy source status may be displayed at the one or more devices.

Abstract: Methods and apparatus for processing packet data are disclosed. An example apparatus includes a plurality of network interfaces configured to send and receive packet data. The example apparatus further includes a switching module coupled with the plurality of network interfaces, the switching module being configured to communicate the packet data to and from the plurality of network interfaces. The example apparatus still further includes a fabric interface controller coupled with the switching module. The example apparatus also includes a virtual fabric interface controller coupled with the fabric interface controller.

Abstract: The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results.

Abstract: According to one general aspect, an apparatus may include an ingress port, a header cache, and a plurality of ingress recursion engines. In some embodiments, the ingress port may be configured to receive a packet that comprises a data portion and a header portion, wherein the header portion comprises at least one header. In various embodiments, the header cache may be configured to store at least a part of the header portion of the packet. In one embodiment, the plurality of ingress recursion engines may be configured to recursively process the header portion, from outer-most header to inner-most header, until an adjacency value for the packet is determined. In some embodiments, each ingress recursion engine may be configured to process a header from the header portion.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: A method for determining whether anomalous activity exists on a network includes receiving a packet from the network, the packet including one or more fields. A classification of the packet based on the one or more fields is determined. A first counter of one or more counters associated with detecting the anomalous activity is incremented based on the classification. An activity metric associated with the one or more counters is determined based on the incrementing, wherein the activity metric is anticipated to fall within a threshold. Whether the anomalous activity exists on the network is determined based on whether the activity metric falls within the threshold.

Abstract: A multi-slice network processor processes a packet in packet slices for transfer over a multi-port network interface such as a switch fabric. The network processor segments a packet into cells having a target size. A group of cells of a common packet form a packet slice which is independently processed by one of a number of parallel processing and storage slices. Load balancing may be used in the selection of processing slices. Furthermore, the network processor may load balance slices across the multi-port network interface to one or more destination slices of another network processor. The multi-slice processor uses post header storage delivery on ingress processing to the multi-port interface thereby reducing temporary storage requirements. The multi-slice network processor may also utilize sequence numbers associated with each packet to ensure that prior to transmission onto a destination network, the packet is in the correct order for a communication flow.

Abstract: An architecture for a multi-port switching device is described having a very regular structure that lends itself to scaling for performance speed and a high level of integration. The distribution of packet data internal to the chip is described as using a cell-based TDM packet transport configuration such as a ring. Similarly, a method of memory allocation in a transmit buffer of each port allows for reassembly of the cells of a packet for storage in a contiguous manner in a queue. Each port includes multiple queues. The destination queue and port for a packet is identified in a multi-bit destination map that is prepended to the start cell of the packet and used by a port to identify packets destined for it. The architecture is useful for a single-chip multi-port Ethernet switch where each of the ports is capable of 10 Gbps data rates.

Abstract: According to an example embodiment, a total offered traffic load for a shared resource within a network switching system may be determined, the total offered traffic load may include, for example, a sum of offered traffic loads from one or more active virtual output queues (VOQs) of the network switching system. A capacity of the shared resource within the network switching system may be determined. A transmission rate from one or more of the active VOQs over the shared resource may be adjusted such that the total traffic load from the active VOQs does not exceed the capacity of the shared resource.

Abstract: According to an example embodiment, a method may include receiving a message, appending a header set to the message, and transmitting the message from an ingress port to an egress port of the network switching system based on the header set. In an example embodiment, the header set may include a variable number of headers, wherein one or more of the headers in the header set includes a next header field to identify a type of header following a current header in the header set. In an example embodiment, the packet may be segmented and transmitted across the switching system as a plurality of cells, where a cell destination address may be a portion (e.g., subset of bits) of the packet destination address.

Abstract: The present invention provides an actuated gate valve including a gate valve housing and an actuating device attached to one end of the gate valve housing. The gate valve housing includes a displaceable valve plate, and the actuating device includes an actuator rod connected to the valve plate so that a force applied to the valve plate by the actuator rod is coincident with a displacement of the valve plate.

Abstract: The present invention consists of a general purpose, software-controlled central processor (CP) augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, which provides the central processor with a numerical summary of the packet format; a packet deconstructor, which extracts designated fields from the packet the positions of which are determined by the central processor according to the packet format; a search engine, which is supplied a lookup index by and returns its results to the central processor; and a packet editor which modifies the packet as determined by the central processor using (in part) information returned from other peripherals. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results.

Abstract: A system and method are disclosed for providing a method of communicating between a media access control (MAC) layer and a physical (PHY) layer. The method includes sending a 100 MHz time-division multiplexed signal on a receive data line and sending a time-division multiplexed receive control signal on a receive control line. A 100 MHz time-division multiplexed signal is sent on a transmit data line and a time-division multiplexed transmit control signal is sent on a transmit control line.

Abstract: A general purpose, software-controlled central processor (CP) can be augmented by a set of task specific, specialized peripheral processors (PPs). The central processor accomplishes its functions with the support of the PPs. Peripheral processors may include but are not limited to a packet parser, a packet deconstructor, a search engine, and a packet editor. At each step in the use of this network processor system, the central processor has an opportunity to intervene and modify the handling of the packet based on its interpretation of PP results. The programmable nature of the CP and the PPs provides the system with flexibility and adaptability.

Abstract: A method, device, and system for positioning a brush of a wafer cleaning system. In the method, device, and system one or more light sources are positioned to generate one or more light beams across a plane. One or more light detectors are positioned to detect when the light beams are interrupted by the brush as it advances toward the plane.

Abstract: Methods and apparatus for providing a network data switch and buffer system are disclosed. In a switch having a memory associated therewith, the memory including a general memory and a plurality of dedicated memory segments, the general memory being available to a plurality of users associated with one or more network devices and each one of the plurality of dedicated memory segments being associated with one of the plurality of users, a method of storing data includes receiving data from a source network device connected to the switch. The data is then stored in a data buffer so that a portion of one of the plurality of dedicated memory segments is allocated when the general memory has been depleted.

Abstract: Methods and apparatus for enabling communication between a source network device and one or more destination network devices are disclosed. The source network device and the one or more destination network devices are connected via an associated interconnect to a switch having a memory associated therewith. One or more messages are composed at the source network device, where the messages include data and control information associated with the data. The messages are then sent to the switch to enable the data and at least a portion of the control information to be stored in the memory associated with the switch, where the data is stored for retrieval by the one or more destination network devices.

Abstract: Provided is a 10Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin). This reduction in the number of pins associated with each port is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional seven-wire interface. As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on nine wires in a conventional seven-wire interface at 10 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 40 MHz, four times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis.