Patents by Inventor Brian R. Bennett
Brian R. Bennett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11852072Abstract: A starter generator located within a sump region of a turbofan engine and coupled to an adapter shaft. The adapter shaft rotationally coupled to the high pressure shaft, forward of a high pressure shaft bearing, and secured by a spanner nut. The engine makes use of two pluralities of electrical conductors, the first extends through an electrical conduit defined by a forward strut extending from the sump region to the outward casing, the second extends axially away from the electric starter. Each of the first plurality of electrical conductors makes reversible contact with a respective one of the second plurality of electrical conductors via an elbow/pin connector, producing a tight turn in area of limited space.Type: GrantFiled: October 28, 2021Date of Patent: December 26, 2023Assignees: Rolls-Royce North American Technologies, Inc., Rolls-Royce CorporationInventors: Melissa Hughes, Brian R. Bennett, Stanford Clemens, Randal Renback
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Publication number: 20220205362Abstract: A rotor assembly adapted for a gas turbine engine includes a shaft, a wheel, and a retaining nut. The shaft extends along an axis and includes a first tapered surface. The wheel is arranged circumferentially around the shaft and includes a second tapered surface. The retaining nut is fastened to the shaft and applies an axial force to the wheel to couple the wheel with the shaft.Type: ApplicationFiled: December 28, 2020Publication date: June 30, 2022Inventors: Kerry J. Lighty, Paul O'Meallie, Brian R. Bennett, Matthew Jordan
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Patent number: 11365630Abstract: A rotor assembly adapted for a gas turbine engine includes a shaft, a wheel, and a retaining nut. The shaft extends along an axis and includes a first tapered surface. The wheel is arranged circumferentially around the shaft and includes a second tapered surface. The retaining nut is fastened to the shaft and applies an axial force to the wheel to couple the wheel with the shaft.Type: GrantFiled: December 28, 2020Date of Patent: June 21, 2022Assignee: Rolls-Royce North American Technologies Inc.Inventors: Kerry J. Lighty, Paul O'Meallie, Brian R. Bennett, Matthew Jordan
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Publication number: 20220049648Abstract: A starter generator located within a sump region of a turbofan engine and coupled to an adapter shaft. The adapter shaft rotationally coupled to the high pressure shaft, forward of a high pressure shaft bearing, and secured by a spanner nut. The engine makes use of two pluralities of electrical conductors, the first extends through an electrical conduit defined by a forward strut extending from the sump region to the outward casing, the second extends axially away from the electric starter. Each of the first plurality of electrical conductors makes reversible contact with a respective one of the second plurality of electrical conductors via an elbow/pin connector, producing a tight turn in area of limited space.Type: ApplicationFiled: October 28, 2021Publication date: February 17, 2022Inventors: Melissa Hughes, Brian R. Bennett, Stanford Clemens, Randal Renback
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Gensets and methods of producing gensets from an engine and generator for hybrid electric propulsion
Patent number: 11008884Abstract: According to one aspect, a genset includes a gas turbine engine having a low pressure shaft wherein the gas turbine engine is adapted to provide mechanical power to a propulsion type load. The genset further includes a generator having an input power shaft wherein the generator is adapted to receive mechanical power to develop electric power. The genset further includes an output power shaft having a first end coupled to the low pressure shaft of the gas turbine and a second end coupled to the input power shaft of the generator and a plurality of struts wherein the first ends of the plurality of struts are coupled to the gas turbine engine and second ends of the plurality of struts are coupled to the generator at locations substantially aligned with a center of gravity of the generator.Type: GrantFiled: August 10, 2018Date of Patent: May 18, 2021Assignees: Rolls-Royce North American Technologies, Inc., Rolls-Royce CorporationInventors: Melissa Hughes, Christopher Banham, Brian R Bennett, Jason L Swindle -
Publication number: 20200049026Abstract: According to one aspect, a genset includes a gas turbine engine having a low pressure shaft wherein the gas turbine engine is adapted to provide mechanical power to a propulsion type load. The genset further includes a generator having an input power shaft wherein the generator is adapted to receive mechanical power to develop electric power. The genset further includes an output power shaft having a first end coupled to the low pressure shaft of the gas turbine and a second end coupled to the input power shaft of the generator and a plurality of struts wherein the first ends of the plurality of struts are coupled to the gas turbine engine and second ends of the plurality of struts are coupled to the generator at locations substantially aligned with a center of gravity of the generator.Type: ApplicationFiled: August 10, 2018Publication date: February 13, 2020Inventors: Melissa Hughes, Christopher Banham, Brian R. Bennett, Jason L. Swindle
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Publication number: 20160092353Abstract: Systems and methods may provide for detecting a pending write operation directed to a target memory region and determining whether the target memory region satisfies a degradation condition in response to the pending write operation. Additionally, the target memory region may be automatically reconfigured as a cold storage region if the target memory region satisfies the degradation condition. In one example, determining whether the target memory region satisfies the degradation condition includes updating the number of write operations directed to the target memory region based on the pending write operation and comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.Type: ApplicationFiled: September 25, 2014Publication date: March 31, 2016Inventors: Robert C. Swanson, Robert W. Cone, Brian R. Bennett, Vladimir Matveyenko, Paul D. Herring, Jordan A. Horwich, Tuan M. Quach, Cuong D. Dinh, Paul M. Leung, Luis E. Valdez, Joseph Hamann, Russell A. Hamann, Michael P. Pham, Caleb C. Molitoris, Kervin T. Ngo, Cory Li, Ola Fadiran, Jason R. Ng, Richard I. Guerin, Jay H. Danver, Chris Kun K. Cheung, Satish R. Natla, Rodel I. Cruz-Herrera
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Patent number: 9054169Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: GrantFiled: October 2, 2014Date of Patent: June 9, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Patent number: 9006708Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.Type: GrantFiled: May 16, 2013Date of Patent: April 14, 2015Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
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Publication number: 20150014745Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: ApplicationFiled: October 2, 2014Publication date: January 15, 2015Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20140339501Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of InwAl1?wAs on a semi-insulating (100) InP substrate, where the InwAl1?wAs is lattice matched to InP, followed by an AlAsxSb1?x buffer layer on the InwAl1?wAs layer, an AlAsxSb1?x spacer layer on the buffer layer, a GaSb quantum well layer on the spacer layer, an AlAsxSb1?x barrier layer on the quantum well layer, an InyAl1?ySb layer on the barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.Type: ApplicationFiled: May 16, 2013Publication date: November 20, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
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Patent number: 8884265Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: GrantFiled: January 16, 2014Date of Patent: November 11, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20140264278Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.Type: ApplicationFiled: January 16, 2014Publication date: September 18, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
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Publication number: 20140217363Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.Type: ApplicationFiled: May 16, 2013Publication date: August 7, 2014Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
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Patent number: 8652959Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: February 1, 2013Date of Patent: February 18, 2014Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Publication number: 20130149845Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: ApplicationFiled: February 1, 2013Publication date: June 13, 2013Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Patent number: 8461664Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: GrantFiled: May 25, 2011Date of Patent: June 11, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A Papanicolaou
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Publication number: 20110297916Abstract: A complementary metal oxide semiconductor (CMOS) device in which a single InxGa1-xSb quantum well serves as both an n-channel and a p-channel in the same device and a method for making the same. The InxGa1-xSb layer is part of a heterostructure that includes a Te-delta doped AlyGa1-ySb layer above the InxGa1-xSb layer on a portion of the structure. The portion of the structure without the Te-delta doped AlyGa1-ySb barrier layer can be fabricated into a p-FET by the use of appropriate source, gate, and drain terminals, and the portion of the structure retaining the Te-delta doped AlyGa1-ySb layer can be fabricated into an n-FET so that the structure forms a CMOS device, wherein the single InxGa1-xSb quantum well serves as the transport channel for both the n-FET portion and the p-FET portion of the heterostructure.Type: ApplicationFiled: May 25, 2011Publication date: December 8, 2011Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Brian R. Bennett, John Bradley Boos, Mario Ancona, James G. Champlain, Nicolas A. Papanicolaou
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Patent number: 7635879Abstract: This invention pertains to heterojunction bipolar transistors containing a semiconductor substrate, a buffer layer of an antimony-based material deposited on the substrate, a sub-collector layer of an antimony-based material deposited on the buffer layer, a collector layer of an antimony-based material deposited on the sub-collector layer, a base layer of an antimony-based material deposited on the collector layer, an emitter layer of an antimony-based material deposited on the base layer, and a cap layer of an antimony-based material deposited on the emitter layer.Type: GrantFiled: September 20, 2005Date of Patent: December 22, 2009Assignee: The United States of America as represented by the Secretary of the NavyInventors: John Bradley Boos, Brian R. Bennett, Paul Campbell, Richard Magno
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Patent number: 7558923Abstract: Some embodiments of the invention include a method of preventing live-lock in a multiprocessor system. The method comprising identifying a first bus transaction attempting to modify a resource and setting a status bit to indicate that a bus transaction attempting to modify the shared resource is pending. The method further comprising retrying each subsequent nonmodifying bus transaction for the shared resource until the status bit is cleared.Type: GrantFiled: December 22, 1999Date of Patent: July 7, 2009Assignee: Intel CorporationInventors: Brian R. Bennett, Stephen S. Chang