Abstract: This invention pertains to an electronic device containing a semi-insulating substrate, a buffer layer of an antimony-based material disposed on said substrate, a channel layer of InAsySb1-y material disposed on said buffer layer, a barrier layer of an antimony-based disposed on said channel layer, and a cap layer of InAsySb1-y material disposed on said barrier layer, wherein the device can have frequency of on the order of 500 GHz and a reduced power dissipation.

Abstract: A memory access system, which includes a read request buffer to receive and reorder requests for memory access. The read request buffer reorders the request to skip a next request when that request is to be delayed. The buffer returns to the skipped request to process the request in a first-in first-out order. The system also includes a buffer allocator to supply buffer addresses for the memory access request, and a control logic to control the reordering of the request.

Abstract: This invention pertains to more sensitive and more stable electronic devices which can sense electrical and magnetic fields. The devices are characterized by InAs channels confined on both sides thereof by a wide band gap AlSb material; protective layers above the AlSb material; modulation doping above the AlSb material; and layers of the InAs channel material containing 1 to 99 mol percent antimony, with the channel material being deposited in the form of alternating monolayers of InSb and InAs, of a ternary mixture of InAsSb.

Abstract: Heterostructure field-effect transistors (HFETs) and other electronic devs are fabricated from a series of semiconductor layers to have reduced impact ionization. On to a first barrier layer there is added a unique second subchannel layer having high quality transport properties for reducing impact ionization. A third barrier layer having a controlled thickness to permit electrons to tunnel through the layer to the subchannel layer is added as a spacer for the fourth main channel layer. A fifth multilayer composite barrier layer is added which has at least a barrier layer in contact with the fourth channel layer and on top a sixth cap layer is applied. The device is completed by adding two ohmic contacts in a spaced apart relationship on the sixth cap layer with a Schottky gate between them which is formed in contact with the fifth barrier layer.

Abstract: A system for facilitating debugging of software running within an information processing unit includes an external trigger state machine which selectively overrides the cacheability attribute of a cache line. An in-circuit emulator (ICE), which is used for debugging purposes, monitors addresses read by and written to a CPU. If an address which is of interest for debugging purposes is detected by the ICE, then the ICE issues a trigger signal. The trigger signal causes the external trigger state machine to designate the cache line associated with the detected address as a non-cacheable operation (i.e., to override the cacheability attribute) . Thus, the data associated with the cache line is written out to the main memory module where the data can be observed by an ICE, rather than to an internal cache memory location where the data would be invisible to an ICE.

Abstract: An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer.

Abstract: A method and apparatus for interfacing multiple integrated circuit chip devices to a system bus includes higher speed portions of a circuit within a primary IC chip and lower speed portions of a circuit within a secondary IC chip. The primary IC chip connects directly to the system bus while the secondary IC chip receives the same bus signals via the primary IC chip after a one clock cycle delay. Both the primary and secondary IC chips are capable of driving signals out onto the system bus when the primary and secondary ICs are part of a bus master circuit. When the primary and secondary ICs act as bus masters, signals are received by the secondary IC chip in the same clock cycle as the primary IC chip receives the signals. Thus, the secondary IC includes a state machine to indicate if the received signals are delayed by one clock cycle or not. In a preferred embodiment, the same pins are used by the primary IC to drive signals through to the secondary IC as to drive signals out onto the system bus.

Abstract: A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.

Abstract: A system for inhibiting interrupts during posted write transfers in a computer system utilizes a buffer to store incoming data and addresses while monitoring incoming addresses to determine if the address is an Input/Output reference to an interrupt controller. If an Input/Output reference to an interrupt controller is detected, a counter is incremented which outputs a logical zero output. A signal indicating a counter value of zero is provided as an input to an AND gate. A second input to the AND gate is provided from an interrupt controller. When the counter contains a non-zero value, a zero input is provided to the AND gate and a zero output is provided to the system bus, regardless of the output from the interrupt controller, inhibiting all further interrupts. Thus, when an interrupt mask is set by a CPU, the present invention immediately inhibits further interrupts from occurring, thereby permitting processing to continue without interruption. As a result, processing time is increased.

Abstract: An improved signaling protocol for use in a multiprocessor system enables concurrent access to a common system bus during an I/O bus access. This reduces the system bus idling time without introducing complexities into the system bus architecture which might otherwise reduce the overall bus bandwidth increase. The improved bus architecture uses a system generated I/O bus busy (IOBUS.sub.-- BSY-) signal to indicate to all of the processors that the I/O bus is in use and that all other I/O requests must be held until the current transaction is completed. By preventing the other processors from executing an I/O request, the system bus does not have to be remain idle and can be used for memory-to-processor and for processor-to-processor transactions while the I/O bus is in use. By reducing the amount of time that the system bus is idle, the overall system bus performance is greatly increased.

Abstract: An improved bus architecture system for use in a multi-processor computer system has a shared address bus and a shared data bus, and has at least two separate memory modules. The system reduces the bus latency time by allowing sequential address requests to different memory modules to begin before previous cycles are terminated. Preferably, the physical memory is mapped onto several separate memory modules which will increase the probability that concurrent address requests from different processors on the common bus are for different memory modules. The processor address determines which memory module contains the data for a new request. If the memory module addressed by the new request differs from the memory module addressed by the current request, the bus controller may issue an early address request for the new data. While the early address request for the new request is being processed, the current bus cycle for the data located in the first memory module is completed on the shared data bus.

Abstract: The invention comprises a pyrolytic process for the deposition of high quality silicon dioxide at temperatures of 100.degree.-330.degree. C. Deposition is achieved by reacting silane and oxygen in the 2-12 torr pressure range, yielding deposition rates of 140 .ANG./min at 300.degree. C. and 50 .ANG./min at 120.degree. C. Measurements of refractive index (1.45-1.46), field strength (3-10.times.10.sup.6 V/cm), and resistivity (10.sup.13 -10.sup.15 -cm) indicate that the oxides are near stoichiometric SiO.sub.2. This technology appears promising the Group IV and Group III-V device applications.