Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes progressively fuller, requests are progressively, using three or more memory access modes, serviced in a manner that increases throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A memory controller receives read requests from a processor into a read queue. The memory controller dynamically modifies an order of servicing the requests based on how many pending requests are in the read queue. When the read queue is relatively empty, requests are serviced oldest first to minimize latency. When the read queue becomes fuller, requests are serviced in a manner that maximizes throughput on a memory bus to reduce the likelihood that the read queue will become full and further requests from the processor would have to be halted.

Abstract: A data processing system includes a coherence directory having a prefetch sector cache and a memory directory array containing a plurality of sectored entries. According to one method, in response to receiving a first directory lookup request specifying a first target address, an entry associated with the target address is accessed in the memory directory array. In response to the access, the coherence directory returns, as a result of the first directory lookup request, contents of a first sector that is identified by the target address as a requested sector. The coherence directory also caches contents of a second sector of the multiple sectors that is a non-requested sector for the first directory lookup request in a prefetch sector cache.

Abstract: A memory controller receives a stream of DMA write operations and enqueues them in a queue enforcing a First-In First-Out (FIFO) order. Prior to processing a particular DMA write operation, the memory controller acquires coherency ownership of a target memory block and stores the result in a low latency array. In response to acquiring coherency ownership, this low latency array is updated to a coherency state signifying coherency ownership by the memory controller. In a pipelined array access, both the low latency array and the second array are accessed and if the lower latency second array indicates the particular coherency state with no collision indication, the memory controller signals that the particular DMA write operation can be performed, where the signaling occurs prior to results being obtained from the higher latency first array at the normal end of the array access pipeline.

Abstract: A multiprocessor data processing system includes a memory controller controlling access to a memory subsystem, multiple processor buses coupled to the memory controller, and at least one of multiple processors coupled to each processor bus. In response to receiving a first read request of a first processor via a first processor bus, the memory controller initiates a speculative access to the memory subsystem and a lookup of the target address in a central coherence directory. In response to the central coherence directory indicating that a copy of the target memory block is cached by a second processor, the memory controller transmits a second read request for the target address on a second processor bus. In response to receiving a clean snoop response to the second read request, the memory controller provides to the first processor the target memory block retrieved from the memory subsystem by the speculative access.

Abstract: In response to a memory access request missing in a central coherence directory of a data processing system, the central coherence directory issues a back-invalidate request and provides an indication of one or more processors possibly caching a copy of a victim memory block associated with a victim memory address. In response to the back-invalidate request, a memory controller initiates a lookup of coherency information for the victim memory address in the central coherence directory and, prior to receipt of the coherency information, speculatively issues a set of back-invalidate commands on one or more of multiple processor buses to invalidate any cached copy of the victim memory block. In response to receipt of the coherency information, the memory controller determines whether the set of speculatively issued back-invalidate commands was under-inclusive, and if not, removes a victim entry associated with the victim memory address from the central coherence directory.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: Embodiments of the invention address deficiencies of the art in respect to cache coherency management and provide a novel and non-obvious method, system and apparatus for silent invalid state transition handling in an SMP environment. In one embodiment of the invention, a cache coherency method can be provided. The cache coherency method can include identifying an invalid state transition for a cache line in a local node, evicting a corresponding cache directory entry for the cache line, forwarding an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line, and relinquishing ownership of the cache line to the home node.

Abstract: Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: Methods and apparatus in a computer system are disclosed for providing a memory controller featuring a dedicated bank sequencer for each memory bank in a memory system. Each bank sequencer controls the dispatch of load and store requests to a central controller such that each request sent to the central controller can be served by the associated memory bank at the time that the central controller receives the request. Since every request received by the central controller is valid from a bank timing standpoint, the central controller is free to process the requests from a predetermined priority basis, without concern for bank availability. This significantly improves the design of the memory controller in the processing system.

Abstract: In a method of controlling stores to and reads from a cache, if a read request is in a read queue, then a read is performed. If no read is in the read queue and if a store request is in a store queue and if an early read predict signal is not asserted, then a store is performed. If no read is in the read queue and if a store request is in the store queue and if the early read predict signal is asserted, if a read is detected a read is then performed. Otherwise, if the early read predict is subsequently de-asserted, then a store is performed.

Abstract: Synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. Addressing errors are detected on the memory interface independent of data ECC, with reduced memory read access latency and improved processor performance. Addressing errors are detected while allowing differentiation between memory addressing failures that are required to stop the system and memory cell failures that allow continued operation. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.

Abstract: A method of transforming and storing data for search and display by a computer system includes formatting and aligning data records of a plurality of objects to a common table mapped format. The formatted and aligned data records are merged and a database is generated therefrom. The database is stored on an optical disc and includes index tables corresponding to searchable data fields. Image data for the objects is compressed and a main compressed image and an image of lesser resolution are randomly stored to a plurality of storage subdirectories on an optical disc. A program for searching and further processing the stored data is also stored on the optical disc with the database and the storage subdirectories. The program for search and display of the data uses an index bar interface for searching the indexed tables. The objects may include real estate properties.