Patents by Inventor Brian Tyrrell
Brian Tyrrell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10893226Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: GrantFiled: June 7, 2019Date of Patent: January 12, 2021Assignee: Massachusetts Institute of TechnologyInventors: Michael W. Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence M Candell
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Patent number: 10771722Abstract: An imaging device is often paired with a readout integrated circuit (ROIC), which provides processing and data transfer functionality. The circuitry of a ROIC is typically specialized to meet the requirements of an application, which limits the ROIC to a few modes of operation and restricts compatibility to only certain types of imaging devices and applications. Furthermore, the circuitry supporting the processing functionality is limited due to size constraints on the ROIC. These shortcomings can be overcome with a field programmable imaging array (FPIA), which can be implemented as an integrated circuit combining customized ROIC sensor interface circuitry with field programmable gate array (FPGA) circuitry to enable post-fabrication definition of ROIC operational modes. An FPIA chip may form part of a three-chip stack that also includes an analog sensor interface chip for analog-to-digital conversion and an imaging device.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: Massachusetts Institute of TechnologyInventors: Peter J. Grossmann, Matthew Stamplis, Kate Thurmer, Brian Tyrrell, Jonathan Frechette
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Publication number: 20200145598Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: ApplicationFiled: June 7, 2019Publication date: May 7, 2020Inventors: Michael W. KELLY, Brian TYRRELL, Curtis COLONERO, Robert BERGER, Kenneth SCHULTZ, James WEY, Daniel MOONEY, Lawrence M. CANDELL
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Patent number: 10425598Abstract: An imaging system uses a dynamically varying coded mask, such as a spatial light modulator (SLM), to time-encode multiple degrees of freedom of a light field in parallel and a detector and processor to decode the encoded information. The encoded information may be decoded at the pixel level (e.g., with independently modulated counters in each pixel), on a read-out integrated circuit coupled to the detector, or on a circuit external to the detector. For example, the SLM, detector, and processor may create modulation sequences representing a system of linear equations where the variables represent a degree of freedom of the light field that is being sensed. If the number of equations and variables form a fully determined or overdetermined system of linear equations, the system of linear equations' solution can be determined through a matrix inverse. Otherwise, a solution can be determined with compressed sensing reconstruction techniques with the constraint that the signal is sparse in the frequency domain.Type: GrantFiled: June 20, 2017Date of Patent: September 24, 2019Assignee: Massachusetts Institute of TechnologyInventors: Joseph Hsuhuan Lin, Michael Kelly, Ralph Hamilton Shepard, III, Brian Tyrrell
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Patent number: 10362254Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: GrantFiled: October 7, 2016Date of Patent: July 23, 2019Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
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Publication number: 20190104269Abstract: An imaging device is often paired with a readout integrated circuit (ROIC), which provides processing and data transfer functionality. The circuitry of a ROIC is typically specialized to meet the requirements of an application, which limits the ROIC to a few modes of operation and restricts compatibility to only certain types of imaging devices and applications. Furthermore, the circuitry supporting the processing functionality is limited due to size constraints on the ROIC. These shortcomings can be overcome with a field programmable imaging array (FPIA), which can be implemented as an integrated circuit combining customized ROIC sensor interface circuitry with field programmable gate array (FPGA) circuitry to enable post-fabrication definition of ROIC operational modes. An FPIA chip may form part of a three-chip stack that also includes an analog sensor interface chip for analog-to-digital conversion and an imaging device.Type: ApplicationFiled: September 28, 2018Publication date: April 4, 2019Applicant: Massachusetts Institute of TechnologyInventors: Peter J. GROSSMANN, Matthew STAMPLIS, Kate THURMER, Brian TYRRELL, Jonathan FRECHETTE
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Publication number: 20170366763Abstract: An imaging system uses a dynamically varying coded mask, such as a spatial light modulator (SLM), to time-encode multiple degrees of freedom of a light field in parallel and a detector and processor to decode the encoded information. The encoded information may be decoded at the pixel level (e.g., with independently modulated counters in each pixel), on a read-out integrated circuit coupled to the detector, or on a circuit external to the detector. For example, the SLM, detector, and processor may create modulation sequences representing a system of linear equations where the variables represent a degree of freedom of the light field that is being sensed. If the number of equations and variables form a fully determined or overdetermined system of linear equations, the system of linear equations' solution can be determined through a matrix inverse. Otherwise, a solution can be determined with compressed sensing reconstruction techniques with the constraint that the signal is sparse in the frequency domain.Type: ApplicationFiled: June 20, 2017Publication date: December 21, 2017Inventors: Joseph Hsuhuan Lin, Michael KELLY, Ralph Hamilton SHEPARD, III, Brian TYRRELL
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Patent number: 9768785Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.Type: GrantFiled: September 10, 2015Date of Patent: September 19, 2017Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis B. Colonero, Lawrence M. Candell, Daniel Mooney
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Publication number: 20170026603Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: ApplicationFiled: October 7, 2016Publication date: January 26, 2017Inventors: MICHAEL KELLY, BRIAN TYRRELL, CURTIS COLONERO, ROBERT BERGER, KENNETH SCHULTZ, JAMES WEY, DANIEL MOONEY, LAWRENCE CANDELL
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Patent number: 9491389Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: GrantFiled: March 21, 2014Date of Patent: November 8, 2016Assignee: Massachusetts Institute of TechnologyInventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
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Patent number: 9159446Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.Type: GrantFiled: November 6, 2013Date of Patent: October 13, 2015Assignee: Massachusetts Institute of TechnologyInventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis Colonero, Lawrence M. Candell, Daniel Mooney
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Publication number: 20140321600Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.Type: ApplicationFiled: November 6, 2013Publication date: October 30, 2014Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: KENNETH I. SCHULTZ, BRIAN TYRRELL, MICHAEL W. KELLY, CURTIS COLONERO, LAWRENCE M. CANDELL, DANIEL MOONEY
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Publication number: 20140197303Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: ApplicationFiled: March 21, 2014Publication date: July 17, 2014Inventors: MICHAEL KELLY, BRIAN TYRRELL, CURTIS COLONERO, ROBERT BERGER, KENNETH SCHULTZ, JAMES WEY, DANIEL MOONEY, LAWRENCE CANDELL
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Patent number: 8692176Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: GrantFiled: November 18, 2011Date of Patent: April 8, 2014Inventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
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Patent number: 8605853Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.Type: GrantFiled: September 8, 2011Date of Patent: December 10, 2013Assignee: Massachusetts Institute of TechnologyInventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis Colonero, Lawrence M. Candell, Daniel Mooney
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Publication number: 20130003911Abstract: Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.Type: ApplicationFiled: September 8, 2011Publication date: January 3, 2013Inventors: Kenneth I. Schultz, Brian Tyrrell, Michael W. Kelly, Curtis Colonero, Lawrence M. Candell, Daniel Mooney
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Publication number: 20120138774Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: ApplicationFiled: November 18, 2011Publication date: June 7, 2012Inventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
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Publication number: 20100226495Abstract: A digital focal plane array includes an all-digital readout integrated circuit in combination with a detector array. The readout circuit includes unit cell electronics, orthogonal transfer structures, and data handling structures. The unit cell electronics include an analog to digital converter. Orthogonal transfer structures enable the orthogonal transfer of data among the unit cells. Data handling structures may be configured to operate the digital focal plane array as a data encryptor/decipherer. Data encrypted and deciphered by the digital focal plane array need not be image data.Type: ApplicationFiled: October 29, 2007Publication date: September 9, 2010Inventors: Michael Kelly, Brian Tyrrell, Curtis Colonero, Robert Berger, Kenneth Schultz, James Wey, Daniel Mooney, Lawrence Candell
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Patent number: 7651821Abstract: A method forms patterns on a substrate by exposing the substrate a first time and exposing the substrate a second time using a mask containing gray-tone features. The gray-tone features locally adjust an exposure dose in regions corresponding to features defined in the primary exposure. Moreover, the gray-tone features enable the forming of features having different critical dimensions on a substrate. The gray-tone features may be implemented as sub-resolution features formed by pixellation. The gray-tone features may also be realized by the local size bias of trim features on the trim mask that have dimensions near the resolution limit of the exposure system. The trim mask containing gray-tone features may have regions with different transmissivities or generate varying illumination intensities.Type: GrantFiled: April 8, 2005Date of Patent: January 26, 2010Assignee: Massachusetts Institute of TechnologyInventors: Brian Tyrrell, Michael Fritze
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Patent number: 7583360Abstract: A method forms a feature pattern on a substrate by exposing the substrate, using a mask having a pattern of features thereon, with illumination having a first set of settings. The substrate is exposed a second time, using the same mask having the pattern of features thereon, with illumination having a second set of settings. The mask having the pattern of features thereon remains stationary between the two illumination exposures of the substrate.Type: GrantFiled: May 23, 2005Date of Patent: September 1, 2009Assignee: Massachusetts Institute of TechnologyInventors: Michael Fritze, Brian Tyrrell