Patents by Inventor Brian W. Amick
Brian W. Amick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9374080Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.Type: GrantFiled: October 20, 2014Date of Patent: June 21, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Brian W. Amick, Gerald R. Talbot, Warren Anderson
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Patent number: 9274938Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.Type: GrantFiled: January 9, 2013Date of Patent: March 1, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Shawn Searles, Nicholas Todd Humphries, Brian W. Amick, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn
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Publication number: 20150130519Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.Type: ApplicationFiled: October 20, 2014Publication date: May 14, 2015Inventors: Brian W. Amick, Gerald R. Talbot, Warren Anderson
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Patent number: 8607104Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.Type: GrantFiled: December 20, 2010Date of Patent: December 10, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Hanwoo Cho, Tahsin Askar, Philip E. Madrid, Guhan Krishnan, Brian W. Amick, Shawn Searles, Ryan J. Hensley
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Patent number: 8373447Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.Type: GrantFiled: November 24, 2010Date of Patent: February 12, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Joseph E. Kidd, Brian W. Amick, Ryan J. Hensley, James R. Magro, Ronald L. Pettyjohn
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Patent number: 8358158Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.Type: GrantFiled: December 21, 2010Date of Patent: January 22, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Brian W. Amick, Ryan J. Hensley, Warren R. Anderson, Joseph E. Kidd
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Patent number: 8356155Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.Type: GrantFiled: October 22, 2010Date of Patent: January 15, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Shawn Searles, Nicholas T. Humphries, Brian W. Amick, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn
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Publication number: 20120159271Abstract: A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Hanwoo Cho, Tahsin Askar, Philip E. Madrid, Guhan Krishnan, Brian W. Amick, Shawn Searles, Ryan J. Hensley
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Publication number: 20120154011Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Brian W. Amick, Ryan J. Hensley, Warren R. Anderson, Joseph E. Kidd
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Publication number: 20120126871Abstract: A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.Type: ApplicationFiled: November 24, 2010Publication date: May 24, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Joseph E. Kidd, Brian W. Amick, Ryan J. Hensley, James R. Magro, Ronald L. Pettyjohn
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Publication number: 20120066445Abstract: A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.Type: ApplicationFiled: October 22, 2010Publication date: March 15, 2012Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Shawn Searles, Nicholas T. Humphries, Brian W. Amick, Richard W. Reeves, Hanwoo Cho, Ronald L. Pettyjohn
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Patent number: 7263628Abstract: A Mobile Subscriber Directory Assistance (MSDA) system including originating carrier center initiating a directory assistance call, a directory assistance center providing a directory assistance service, and a search environment. The search environment includes an aggregated pointer database and at least one directory number resolution database. A caller requesting a telephone number is connected to a directory assistance service center where search criteria for the requested number are taken. The requested number is identified by searching the aggregated pointer database and the directory number resolution database. The caller is connected to the identified telephone number without releasing this identified telephone number.Type: GrantFiled: March 3, 2003Date of Patent: August 28, 2007Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Aninda K. Roy, Pradeep R. Trivedi, Brian W. Amick
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Patent number: 7193447Abstract: A sense amplifier latch that is operable to interface with high common-mode input voltages with wide ranges for all process variations. The sense amplifier latch comprises a cross-coupled latch having first and second rail signals; a pre-charge device; an equalization device; pass devices for enabling input devices to receive pad and reference inputs. In the present invention, the input devices comprise push-pull impedance dividers are used to preserve the input difference voltage while dramatically lowering the common-mode output voltage. The outputs of the impedance dividers are fed to the cross-coupled latch of the sense amplifier using n-channel pass gates.Type: GrantFiled: May 6, 2004Date of Patent: March 20, 2007Assignee: Sun Microsystems, Inc.Inventors: Shao H. Liu, Tri K. Tran, Brian W. Amick
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Patent number: 7109767Abstract: A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.Type: GrantFiled: July 12, 2004Date of Patent: September 19, 2006Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Aparna Ramachandran, Dong J. Yoon, Tri K. Tran, Gajendra P. Singh, Claude R. Gauthier
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Patent number: 7110461Abstract: A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit includes a circuit that temporally expands at least a portion of the pre-coded data signal. The portion of the temporally expanded data signal is latched by the receiving circuit.Type: GrantFiled: July 18, 2002Date of Patent: September 19, 2006Assignee: Sun Microsystems, Inc.Inventors: Aninda K. Roy, Claude R. Gauthier, Brian W. Amick
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Patent number: 7062688Abstract: A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.Type: GrantFiled: July 16, 2002Date of Patent: June 13, 2006Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Aninda K. Roy, Brian W. Amick, Dean Liu
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Patent number: 7062662Abstract: An apparatus for canceling an effect of power supply resonance is provided. The effect of power supply resonance is a variation in power supply voltage potential. This variation may substantially affect an output buffer by causing the output buffer's output to sag below desired values. A voltage regulating circuit is coupled to power supply lines local to the output buffer where the voltage regulating circuit is most effective in reducing voltage potential variation. An exemplary voltage regulating circuit is provided that uses charge-pumped capacitors to raise the power supply voltage potential when it falls below a desired value. A second example of a voltage regulating circuit uses charge-pumped capacitors to lower the power supply voltage potential when it rises above a desired value.Type: GrantFiled: December 23, 2002Date of Patent: June 13, 2006Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Aninda K. Roy, Brian W. Amick
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Patent number: 7043379Abstract: A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.Type: GrantFiled: October 22, 2002Date of Patent: May 9, 2006Assignee: Sun Microsystems, Inc.Inventors: Claude R. Gauthier, Aninda K. Roy, Brian W. Amick
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Patent number: 7043683Abstract: A data transmission update technique for use in a low power mode and/or a low activity mode of a computer system or a portion thereof is provided. When in the low power mode and/or the low activity mode, the technique initiates a testing of data transmissions, the results of which are used to adjust the timing of data receipt such that accurate and timely date communications are facilitated.Type: GrantFiled: February 7, 2003Date of Patent: May 9, 2006Assignee: Sun Microsystems, Inc.Inventors: Brian W. Amick, Claude R. Gauthier, Aninda Roy
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Patent number: 7017086Abstract: A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.Type: GrantFiled: June 18, 2002Date of Patent: March 21, 2006Assignee: Sun Microsystems, Inc.Inventors: Aninda K. Roy, Claude R. Gauthier, Brian W. Amick
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Patent number: 4963241Abstract: An electrolytic cell which comprises at least one anode and at least one cathode, an inlet channel through which liquor may be charged to the electrolytic cell, and an outlet channel through which liquor may be removed from the electrolytic cell, in which the outlet channel is operatively connected to the inlet channel, and in which the inlet channel comprises an ejector. The inlet and outlet channels may be formed in a unit made up of a plurality of shaped sheets, e.g. of electrically non-conducting plastics material, which together form the inlet and outlet channels.Type: GrantFiled: January 30, 1989Date of Patent: October 16, 1990Assignee: Imperial Chemical Industries PLCInventor: Keith Brattan