Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A method for quantifying effects of resonance in an integrated circuit's power distribution network is provided. The power distribution network includes a first power supply line and a second power supply line to provide power to the integrated circuit. Test ranges are selected for two test parameters, reference voltage potential of a receiver and data transmission frequency of the integrated circuit. At each combination of the two test parameters, bit patterns are transmitted by the integrated circuit to the receiver. A comparison is made between the transmitted bits and the received bits to determine whether the transmitted bits were correctly received. The comparison may be used to determine and report a range of values for the reference voltage potential and data transmission frequency that allow the transmitted bits to be correctly received.

Abstract: An apparatus for compensating for the effects of resonance in an integrated circuit's power distribution network is provided. A resonance detector monitors transmissions from the integrated circuit for certain bit patterns that may excite the power distribution network at a specific frequency and cause power supply resonance. Power supply resonance causes an increase in power supply impedance. When offending transmissions are detected, the resonance detector activates a damping element on the integrated circuit which dampens the resonance. The damping element is a resistive device between two power supply lines that decreases power supply impedance when activated.

Abstract: A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ ground reference voltage is provided. The ‘virtual’ ground voltage reference, being greater than a zero volt ground voltage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ ground reference voltage off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by an analog delay line.

Abstract: A source synchronous interface determines an amount of delay for an incoming data signal and a phase offset for a latch device that latches the incoming data signal. A delay locked loop may be a dual loop delay locked loop, in which case, the loops may use a low jitter, local clock signal and an input clock signal that was transmitted with the data signal. The low jitter, local clock signal may provide a stable source from which to derive good clock signal edge transitions. The input clock signal may be used to determine the long term clock signal drift. A finite state machine within the dual loop delay locked loop may provide the necessary information for the amount of delay and the phase offset. The delay of the incoming data signal is produced by a digital delay line.

Abstract: A method for reducing noise in an I/O system has been developed. The method includes powering up the I/O supply and activating or inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the I/O power supply, and is controllable such that the resistance can be selectively switched ‘on’ and/or ‘off.

Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: A method and apparatus for post-fabrication calibration and adjustment of a phase locked loop leakage current is provided. The calibration and adjustment system includes an adjustment circuit that adjusts a leakage current offset circuit to compensate for the leakage current of a capacitor. The capacitor connects to a control voltage of the phase locked loop. Such control of the leakage current in the phase locked loop allows a designer to achieve a desired phase locked loop operating characteristic after the phase locked loop has been fabricated. A representative value of the amount of compensation desired in the leakage current may be stored and subsequently read to adjust the phase locked loop.

Abstract: A method and apparatus for enlarging data eyes in a wireline communication system involves pre-coding a data signal before transmission to generate a constant frequency characteristic independent of a state of the pre-coded data signal. The receiving circuit includes a circuit that temporally expands at least a portion of the pre-coded data signal. The portion of the temporally expanded data signal is latched by the receiving circuit.

Abstract: A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.

Abstract: A technique for adjusting a communication system involves a plurality of links where each link includes a data line adapted to transmit a data signal and a clock line adapted to transmit a clock signal. A test circuit connects to the plurality of links where the test circuit tests at least one of the plurality of links. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal of the one of the plurality of links based on an offset where the adjustment circuit adjusts a timing of the adjustable clock signal relative to the data signal of the one of the plurality of links. The test circuit is adapted to perform a round-robin testing of the plurality of the links.

Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: An adjustment and calibration system for post-fabrication treatment of a phase locked loop input receiver is provided. The adjustment and calibration system includes at least one adjustment circuit, to which the phase locked loop input receiver is responsive, and a storage device that selectively stores control information (1) associated with a state of the adjustment circuit and/or (2) from a tester that writes such control information to the storage device, where the control information stored in the storage device is subsequently selectively read out in order to adjust the adjustment circuit to a state corresponding to the control information.

Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.

Abstract: A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.