Abstract: A computer system, processor, and method for processing information is disclosed. The system, processor and/or method includes at least one computer processor; a register file associated with the at least one processor, the register file having a plurality of entries for storing data where a whole entry has two halves, the register file having multiple ports to write data to the register file and multiple ports to read data from the register file; and one or more execution units associated with the register file, the execution units configured to read data from the register file and to write data to the register file, wherein the processor is configured to write either scalar data or vector data to a single register file entry.

Abstract: Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor; a main register file associated with the at least one processor, the main register file having a plurality of entries for storing data, one or more write ports to write data to the main register file entries, and one or more read ports to read data from the main register file entries; one or more execution units including a dense math execution unit; and at least one accumulator register file having a plurality of entries for storing data. The results of the dense math execution unit in an aspect are written to the accumulator register file, preferably to the same accumulator register file entry multiple times, and the data from the accumulator register file is written to the main register file.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a hypervisor, that consumption of memory controller resources, by a plurality of processing threads, is above a threshold quantity, wherein respective processing threads of the plurality of processing threads control respective prefetch settings; and responsive to determining that the consumption of the memory controller resources is above the threshold quantity, modifying individual memory controller usage of at least one of the plurality of processing threads such that the consumption of the memory controller resources is reduced below the threshold quantity.

Abstract: A system and/or method for processing information is disclosed that has at least one processor; a register file associated with the processor, the register file sliced into a plurality of STF blocks having a plurality of STF entries, and in an embodiment, each STF block is further partitioned into a plurality of sub-blocks, each sub-block having a different portion of the plurality of STF entries; and a plurality of execution units configured to read data from and write data to the register file, where the plurality of execution units are arranged in one or more execution slices. In one or more embodiments, the system is configured so that each execution slice has a plurality of STF blocks, and alternatively or additionally, each of the plurality of execution units in a single execution slice is assigned to write to one, and preferably only one, of the plurality of STF blocks.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: A computer processor includes an issue queue to receive an instruction, and one or more execution units to generate a condition code bit corresponding to the instruction. A branch condition queue is in signal communication with the issue queue, and receives the instruction from the issue queue before the at least one execution unit generates the condition code bit.

Abstract: A computer system, processor, and method for processing information is disclosed that includes allocating a prefetch stream; providing a protection bubble to a plurality of cachelines for the allocated prefetch stream; accessing a cacheline; and preventing allocation of a different prefetch stream if the accessed cacheline is within the protection bubble. The system, processor and method in an aspect further includes providing a safety zone to a plurality of cachelines for the allocated prefetch stream, and advancing the prefetch stream if the accessed cacheline is one of the plurality of cachelines in the safety zone. In an embodiment, the number of cachelines within the safety zone is less than the number of cachelines in the protection bubble.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, the register file having a plurality of entries for storing data and sliced into a plurality of register banks, each register bank having a portion of the plurality of entries for storing data, one or more write ports to write data to the register file entries, and a plurality of read ports to read data from the register file entries; one or more read multiplexors associated with one or more read ports of each register bank and configured to receive data from the respective register banks; and one or more write multiplexors associated with one or more of the register banks.

Abstract: Managing application execution by receiving a store instruction, including a store instruction itag and store instruction address, creating a hash of the store instruction address, receiving a load instruction and matching a hash of a store instruction address associated with the load instruction with the hash of the store instruction address associated with the store instruction. The store instruction itag is sent to an instruction sequencing unit (ISU). The ISU delays execution of the load instruction according to the received itag.

Abstract: A method, system, and/or processor for processing data is disclosed that includes processing a parent stream; detecting a branch instruction in the parent stream; activating an additional child stream; setting a copy select vector of the child stream to be the same as the copy select vector of the parent stream; dispatching instructions for the parent stream and the additional child stream, and executing the parent stream and the additional child stream on different execution slices. In an aspect, the method further includes setting the copy select bits in the copy select vector for the child stream to equal the copy select bits in the copy select vector for the parent stream. A first parent mapper copy in an embodiment is associated and used in connection with executing the parent stream and a second different child mapper copy is associated and used in connection with executing the additional child stream.

Abstract: An example computer-implemented method includes receiving a first value, a second value, a third value, and a fourth value, wherein the first value, the second value, the third value, and the fourth value are 16-bit or smaller precision floating-point numbers. The method further includes multiplying the first value and the second value to generate a first product, wherein the first product is a 32-bit floating-point number. The method further includes multiplying the third value and the fourth value to generate a second product, wherein the second product is a 32-bit floating-point number. The method further includes summing the first product and the second product to generate a summed value, wherein the summed value is a 32-bit floating-point number. The method further includes adding the summed value to an addend value to generate a result value, wherein the addend value and the result value are 32-bit floating-point numbers.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A number of rank updates of a result matrix to store in an accumulator register having a predetermined size are determined, where the number of rank updates is based on the first precision and the first shape of the first input matrix, the second precision and the second shape of the second input matrix, and the predetermined size of the accumulator register. A plurality of linear algebra operations is repeated in parallel within the compute array to update the result matrix in the accumulator register based on the first input matrix, the second input matrix, and the number of rank updates.

Abstract: Embodiments of the present invention are directed to a new instruction set extension and a method for providing 3D lane predication for matrix operations. In a non-limiting embodiment of the invention, a first input matrix having m rows and k columns and a second input matrix having k rows and n columns are received by a compute array of a processor. A three-dimensional predicate mask having an M-bit row mask, an N-bit column mask, and a K-bit rank mask is generated. A result matrix of up to m rows, up to n columns, and up to k rank updates is determined based on the first input matrix, the second input matrix, and the predicate mask.

Abstract: A processor unit for multiply and accumulate (“MAC”) operations is provided. The present invention may include the processor unit having a plurality of MAC units for performing a set of MAC operations. The present invention may include each MAC unit having an execution unit and a one-write one-read (“1W/1R”) register file, where the 1W/1R register file may have at least one accumulator. The present invention may include the execution unit of each MAC unit being configured to perform a subset of MAC operations by computing a product of a set of values received from another register file of the processor unit and adding the computed product to the at least one accumulator. The present invention may include each MAC unit being configured to perform the respective subset of MAC operations in a single clock cycle.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one processor having a main register file, the main register file having a plurality of entries for storing data; one or more execution units including a dense math execution unit; and at least one accumulator register file, the at least one accumulator register file associated with the dense math execution unit. The processor in an embodiment is configured to process data in the dense math execution unit where the results of the dense math execution unit are written to a first group of one or more accumulator register file entries, and after a checkpoint boundary is crossed based upon, for example, the number “N” of instructions dispatched after the start of the checkpoint, the results of the dense math execution unit are written to a second group of one or more accumulator register file entries.

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; a Page Walk Cache (PWC) for storing page directory entries; and a memory controller configured to control accesses to the memory devices. The processor in an embodiment is configured to send to the memory controller a page directory base and a plurality of memory offsets; and receive from the memory controller and store in the PWC at least one of the page directory entries. The memory controller is configured to: combine a first level page directory entry with a second level memory offset; read from memory a second page directory entry using the first level page directory entry and the second level memory offset; and send to the processor at least one of the page directory entries and a page table entry (PTE).

Abstract: An information handling system and method for translating virtual addresses to real addresses including a processor for processing data; memory devices for storing the data; and a memory controller configured to control accesses to the memory devices, where the processor is configured, in response to a request to translate a first virtual address to a second physical address, to send from the processor to the memory controller a page directory base and a plurality of memory offsets. The memory controller is configured to: read from the memory devices a first level page directory table using the page directory base and a first level memory offset; combine the first level page directory table with a second level memory offset; and read from the memory devices a second level page directory table using the first level page directory table and the second level memory offset.

Abstract: A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.