Abstract: Managing program instruction execution by receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address and creating a first OSC table entry according to the first itag and first instruction address. Further, receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address and creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag, then appending the second OSC table entry according to an itag delta between the second itag and a third itag, and providing an itag delta from the second OSC table entry to an instruction sequencing unit (ISU).

Abstract: Managing application execution by receiving a store instruction, including a store instruction itag and store instruction address, creating a hash of the store instruction address, receiving a load instruction and matching a hash of a store instruction address associated with the load instruction with the hash of the store instruction address associated with the store instruction. The store instruction itag is sent to an instruction sequencing unit (ISU). The ISU delays execution of the load instruction according to the received itag.

Abstract: Managing program instruction execution by receiving a first OSC (operand store compare) instruction, the first OSC instruction comprising a first itag and a first instruction address and creating a first OSC table entry according to the first itag and first instruction address. Further, receiving a second OSC instruction, the second OSC instruction comprising a second itag and a second instruction address and creating a second OSC table entry according to the second itag and an itag delta between the first itag and the second itag, then appending the second OSC table entry according to an itag delta between the second itag and a third itag, and providing an itag delta from the second OSC table entry to an instruction sequencing unit (ISU).

Abstract: A method and apparatus for garbage collection is disclosed herein. The method includes specifying a load-monitored region within a memory managed by a run-time environment, enabling a load-monitored event-based branch configured to occur responsive to executing a first type of CPU instruction to load a pointer that points to a first location in the load-monitored region, performing a garbage collection process in background without pausing executing in the run-time environment, executing a CPU instruction of the first type to load a pointer that points to the first location in the load-monitored region, and responsive to triggering a load-monitored event-based branch, moving an object pointed to by the pointer with a handler from the first location in memory to a second location in memory.

Abstract: A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.

Abstract: A method comprises a cache manager receiving reference attributes associated with network data and selecting a replacement data location of a cache to store cache-line data associated with the network data. The replacement data location is selected based on the reference attributes and an order of reference states stored in a replacement stack of the cache. The stored reference states are associated with respective cached-data stored in the cache and based on reference attributes associated with respective cached-data. The reference states are stored in the replacement stack based on a set of the reference attributes and the stored reference states. In response to receiving reference attributes, the cache manager can modify a stored reference state, determine a second order of the state locations, and store a reference state in the replacement stack based on the second order. A system can comprise a network computing element having a cache, a cache manager, and a replacement stack.

Abstract: A computing system includes an issue queue and a microprocessor. The issue queue receives a fused instruction, which includes a first instruction portion fused with a second instruction portion different from the first instruction portion. The microprocessor assigns a first instruction tag (ITAG) to the first instruction portion and a second ITAG to the second instruction portion. The microprocessor determines a first bit that represents the first ITAG, inverts the first bit to determine a second bit that represents the second ITAT, and determines an availability of one or more sources of a second instruction different from the fused instruction based at least in part on the first bit or the second bit.

Abstract: Operation of a multi-slice processor that includes a plurality of execution slices and an instruction sequencing unit. Operation of such a multi-slice processor includes: receiving, at the instruction sequencing unit, a load instruction indicating load address data and a load data length; determining a previous store instruction in an issue queue such that store address data for the previous store instruction corresponds to the load address data, wherein the previous store instruction corresponds to a store data length; and generating, in dependence upon the store data length matching the load data length, an indication in the issue queue that indicates a dependency between the load instruction and the previous store instruction.

Abstract: An approach is disclosed that in one or more embodiments includes receiving an indicator to issue an out-of-order instruction or a type of out-of-order instruction in-order; receiving a first instruction; determining whether the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction; writing, in response to determining that the first instruction corresponds to the indicated out-of-order instruction or the type of out-of-order instruction, an instruction identifier and a dependent instruction opcode into a first queue and an issue queue of the processor; receiving at least one subsequent instruction; determining whether an instruction opcode of the subsequent instructions matches the dependent instruction opcode of the first instruction; and writing, in response to determining the instruction opcode of the subsequent instruction matches the dependent instruction opcode of the instruction, a dependent instruction identifier for the subsequent instruction

Abstract: A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes generating workload information of a performance base test; determining characteristics of the workload information; determining one or more constraints that can cause behavioral changes to a design of the processor; combining the determined characteristics and the determined one or more constraints to generate one or more example constraints; testing the one or more example constraints in one or more example performance tests; and generating one or more performance benchmarks for the performance base test and the one or more example performance tests.

Abstract: Techniques for parallel execution of instructions in an instruction set are described. The techniques include determining a plurality of instruction streams and paths for a branch in an instruction set and executing the determined paths in parallel such that a mis-predicted path does not cause significant mis-prediction penalties.

Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.

Abstract: Converting program instructions for two-stage processors including receiving, by a preprocessing unit, a group of program instructions; determining, by the preprocessing unit, that at least two of the group of program instructions can be converted into a single combined instruction; converting, by the preprocessing unit, the at least two program instructions into the single combined instruction comprising an extension opcode, wherein the extension opcode indicates, to an execution unit, a format of the single combined instruction; and sending, by the preprocessing unit, the single combined instruction to the execution unit.

Abstract: A method comprises receiving input reference attributes from a data reference interface and selecting a replacement data location of a cache to store data. The replacement data location is selected based on the input reference attributes and reference states associated with cached-data stored in data locations of the cache and an order of state locations of a replacement stack storing the reference states. The reference states are based on reference attributes associated with the cached-data and can include a probability count. The order of state locations is based on the reference states and the reference attributes. In response to receiving some input reference attributes, reference states stored in the state locations can be modified and a second order of the state locations can be determined. A reference state can be stored in the replacement stack based on the second order.

Abstract: A computing system includes an issue queue and a microprocessor. The issue queue receives a fused instruction, which includes a first instruction portion fused with a second instruction portion different from the first instruction portion. The microprocessor assigns a first instruction tag (ITAG) to the first instruction portion and a second ITAG to the second instruction portion. The microprocessor determines a first bit that represents the first ITAG, inverts the first bit to determine a second bit that represents the second ITAT, and determines an availability of one or more sources of a second instruction different from the fused instruction based at least in part on the first bit or the second bit.

Abstract: A processor reads at least one instruction comprising at least one of a branch instruction and a non-branch instruction. In response to the branch instruction comprising a conditional branch instruction and set in dynamic mode, the processor dynamically predicts a branch path as taken or not taken. The processor, in response to the instruction fetch unit set in static mode for a conditional branch instruction and static branch prediction setting bits received with the conditional branch instruction specifying static branch prediction, statically sets the branch path as taken or not taken according to the static branch prediction setting bits received with the branch instruction. The processor selectively sets the operation of the processor temporarily from the dynamic mode to the static mode only in response to detecting a type of the at least one instruction matches a type of instruction qualifying to trigger static branch prediction.

Abstract: A processor, system and/or techniques are disclosed for prefetching data streams in a processor. A prefetcher issues a plurality of requests to pre-fetch data from a stream in a plurality of streams; evaluates a confidence level of at least the first request based on an amount of confirmations observed in the stream; and assigns at least a first more aggressive prefetching ramping mode or a second less aggressive prefetching ramping mode based upon the confidence level of a thread associated with the prefetch request, wherein the prefetcher has one or more probationary states and is configured to transition between the first and second prefetching ramp mode by entering at least one of the probation states wherein the prefetcher continues to operate in the first prefetching ramp mode. In another aspect, the prefetcher may transition to the one or more probation states after a number of cycles.

Abstract: A cache comprises data locations in a storage medium and a set of reference states corresponding to the data locations and abased on reference attributes associated with data stored in the data locations. The cache receives reference information associated with a data reference and selects a data location to store data reference based on a reference state corresponding to the data location. The cache modifies reference states based on reference attributes associated with data references. A method of managing a cache includes receiving reference information associated with a data reference and selecting a data location in a storage medium to store data based on reference attributes associated with data stored in the selected data location. The method can include modifying reference states in response to receiving reference information. The cache and the method can include a count, based on reference attributes, in a reference state.

Abstract: A method comprises receiving input reference attributes from a data reference interface and selecting a replacement data location of a cache to store data. The replacement data location is selected based on the input reference attributes and reference states associated with cached-data stored in data locations of the cache and an order of state locations of a replacement stack storing the reference states. The reference states are based on reference attributes associated with the cached-data and can include a probability count. The order of state locations is based on the reference states and the reference attributes. In response to receiving some input reference attributes, reference states stored in the state locations can be modified and a second order of the state locations can be determined. A reference state can be stored in the replacement stack based on the second order.

Abstract: A computer system, processor, and method for processing information is disclosed that includes allocating a prefetch stream; providing a protection bubble to a plurality of cachelines for the allocated prefetch stream; accessing a cacheline; and preventing allocation of a different prefetch stream if the accessed cacheline is within the protection bubble. The system, processor and method in an aspect further includes providing a safety zone to a plurality of cachelines for the allocated prefetch stream, and advancing the prefetch stream if the accessed cacheline is one of the plurality of cachelines in the safety zone. In an embodiment, the number of cachelines within the safety zone is less than the number of cachelines in the protection bubble.