Patents by Inventor Brijesh Tripathi

Brijesh Tripathi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160351138
    Abstract: An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 1, 2016
    Inventors: Chaohao Wang, Brijesh Tripathi, Christopher Philip Alan Tann, David S. Zalatimo, Guy Cote, Hao Nan, Marc Albrecht, Paolo Sacchetto, Sandro H. Pintz
  • Patent number: 9495926
    Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 15, 2016
    Assignee: Apple Inc.
    Inventors: Brijesh Tripathi, Peter F. Holland, Arthur L. Spence, Axel B. Schumacher, David A. Hartley
  • Patent number: 9489712
    Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: November 8, 2016
    Assignee: NVIDIA Corporation
    Inventors: Duncan A. Riach, Michael A. Ogrinc, Brijesh Tripathi, Wayne D. Young
  • Publication number: 20160307540
    Abstract: Systems, apparatuses, and methods for performing linear scaling in a display control unit. A display control unit receives source image data that has already been gamma encoded with an unknown gamma value. The display control unit includes a hard-coded LUT storing a gamma curve of a first gamma value which is used to perform a degamma operation on the received source image data. Even if the first gamma value used to perform the degamma operation is different from the gamma value used to gamma encode the source image data, fewer visual artifacts are generated as compared with not performing a degamma operation. After the degamma operation is performed, the source image data may be linearly scaled.
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Inventors: Peter F. Holland, Brijesh Tripathi, Guy Cote
  • Patent number: 9471955
    Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 18, 2016
    Assignee: Apple Inc.
    Inventors: Peter F. Holland, Brijesh Tripathi, Dinesh M. Shedge
  • Publication number: 20160293137
    Abstract: Systems, apparatuses, and methods for passing source pixel data through a display control unit. A display control unit includes N-bit pixel component processing lanes for processing source pixel data. When the display control unit receives M-bit source pixel components, wherein ‘M’ is greater than ‘N’, the display control unit may assign the M-bit source pixel components to the N-bit processing lanes. Then, the M-bit source pixel components may passthrough the pixel component processing elements of the display control unit without being modified.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Brijesh Tripathi, Peter F. Holland, Guy Cote
  • Publication number: 20160292094
    Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 6, 2016
    Inventors: Robert E. Jeter, Brijesh Tripathi, Kiran Kattel, Rakesh L. Notani, Fabien S. Faure, Sukalpa Biswas, Kai Lun Hsiung, Neeraj Parik, Venkata Ramana Malladi, Shiva Kumar, Chaitanya Polapragada, Allen Kim
  • Publication number: 20160291625
    Abstract: An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Inventors: Brijesh Tripathi, Eric G. Smith, Erik P. Machnicki, Jung Wook Cho, Khaled M. Alashmouny, Kiran B. Kattel, Vijay M. Bettada, Bo Yang, Wenlong Wei
  • Publication number: 20160274690
    Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Brijesh Tripathi, Jean-Pierre S. Guillou
  • Publication number: 20160155399
    Abstract: Systems, apparatuses, and methods for preventing charge accumulation on a display panel of a display. A display pipeline is configured to drive a display using a variable frame refresh rate. The display may also be driven by a polarity inversion cadence to alternate the polarity on the display panel on back-to-back frames. In some cases, the frame refresh rate cadence, as specified in frame packets which contain configuration data for processing corresponding frames, can cause a charge accumulation on the display panel if an odd number of frames are displayed at a first frame refresh rate before switching to a second frame refresh rate. Accordingly, in these cases, the display pipeline may override the frame refresh rate setting for a given frame to cause an even number of frames to be displayed at the first frame refresh rate.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 2, 2016
    Inventors: Brijesh Tripathi, Peter F. Holland, Arthur L. Spence, Axel B. Schumacher
  • Patent number: 9355585
    Abstract: An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: May 31, 2016
    Assignee: APPLE INC.
    Inventors: Brijesh Tripathi, Jean-Pierre Guillou
  • Patent number: 9336563
    Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: May 10, 2016
    Assignee: Apple Inc.
    Inventors: Joseph P. Bratt, Peter F. Holland, Shing Horng Choo, Timothy J. Millet, Brijesh Tripathi
  • Publication number: 20160092010
    Abstract: Synchronization of display functions and various touch, stylus and/or force sensing functions for devices including a variable refresh rate (VRR) display is disclosed. In some examples, touch, stylus and/or force sensing functions can be synchronized with display frames and a display refresh rate can be adjusted by extended blanking of the display for one or more display frames. In other examples, touch, stylus and/or force sensing functions can be synchronized with display sub-frames and a display refresh rate can be adjusted by extended blanking of the display for one or more display sub-frames. Pre-warning synchronization signals can be generated to prepare one or more scan controllers to implement the appropriate scan events during and after extended blanking periods. Latency between the scan results and the corresponding image on the display can be corrected in software and/or firmware by time-stamping scan results or by dropping scan results from uncompleted scans.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Manu AGARWAL, Christopher Tann, Brijesh Tripathi, Martin Paul Grunthaner
  • Patent number: 9286855
    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The sink processor may be operable to send a synchronization signal to the source processor through the interface. The source processor may be operable, dependent upon the synchronization signal, to send data to the sink processor.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: March 15, 2016
    Assignee: Apple Inc.
    Inventor: Brijesh Tripathi
  • Publication number: 20160071485
    Abstract: Systems, apparatuses, and methods for synchronizing backlight adjustments to frame updates in a display pipeline. A change in the ambient light is detected and as a result, backlight settings are adjusted. To offset a reduction in the backlight, the color intensity in the frames is increased. While the change in ambient light is detected asynchronously, the adjustment to the backlight settings and color intensity is synchronized to a frame update via a virtual channel for the auxiliary channel of the display interface.
    Type: Application
    Filed: September 4, 2014
    Publication date: March 10, 2016
    Inventors: Brijesh Tripathi, Peter F. Holland, Marc Albrecht, Christopher P. Tann
  • Publication number: 20150371607
    Abstract: Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 24, 2015
    Inventors: Peter F. Holland, Brijesh Tripathi, Dinesh M. Shedge
  • Publication number: 20150362947
    Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Inventor: Brijesh Tripathi
  • Publication number: 20150362980
    Abstract: A system on a chip (SOC) may include a component that remains powered when the remainder of the SOC is powered off. The component may be configured to power up other components of the SOC while keeping the central processing unit (CPU) processors powered down, in order to perform a task assigned to such other component(s). The always-on component may further include a processor, in some embodiments, which may interact with the other components to perform the task. In an embodiment, the processor within the always-on component may execute operating system (OS) software to interact with the other components while the CPU processors are powered down.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 17, 2015
    Inventor: Brijesh Tripathi
  • Publication number: 20150356050
    Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.
    Type: Application
    Filed: August 14, 2014
    Publication date: December 10, 2015
    Inventors: Michael J. Smith, Josh P. de Cesare, Brijesh Tripathi, Derek Iwamoto, Shane J. Keil
  • Publication number: 20150355762
    Abstract: Systems, apparatuses, and methods for performing mid-frame blanking. A first portion of a frame is driven to a display and then a first mid-frame blanking interval is generated. Following this first mid-frame blanking interval, a second portion of the frame is driven to the display, followed by a second mid-frame blanking interval, followed by a third portion of the frame, and so on. Any number of mid-frame blanking intervals may be introduced in a given frame. During each mid-frame blanking interval, touch sensing is performed to detect touch events on the screen for in-cell touch type displays. For displays with touch sensors electrically separated from the display common voltage layer, special sense scan steps are performed during mid-frame blanking intervals. By performing touch sensing or special sense scan steps during a frame rather than only at the end of a frame, the performance of touch sensing is improved.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 10, 2015
    Inventors: Brijesh Tripathi, Manu Agarwal, Peter F. Holland