Abstract: In an approach, using a biomedical device, a processor stimulates a cell sample. A processor senses, based on feedback from at least two chemical sensors of the biomedical device, the presence of at least two types of biomolecules released by the cell sample. A processor records, using a computer chip of the device, data collected by the at least two chemical sensors. A processor sends, using an antenna of the biomedical device, the recorded data to a remote server.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first magnetic tunnel junction stack, forming a spin conducting layer on the first magnetic tunnel junction stack, forming a second magnetic tunnel junction stack on the spin conducting layer, and forming a dielectric spacer layer on surfaces of the spin conducting layer and the second magnetic tunnel junction stack. The second magnetic tunnel junction stack has a width that is less than a width of the first magnetic tunnel junction stack. Also, a width of the spin conducting layer increases in a thickness direction from a first side of the spin conducting layer adjacent to the second magnetic tunnel junction stack to a second side of the spin conducting layer adjacent to the first magnetic tunnel junction stack.

Abstract: In an approach, a biomedical device comprises at least one electrode, wherein the at least one electrode is coupled with a computer chip; at least two chemical sensors, wherein the at least two chemical sensors are coupled with the computer chip; the computer chip, wherein the computer chip comprises: a semiconductor substrate, and a processor; a microfluidic structure, wherein the microfluidic structure is an inert elastomeric polymer; a power supply device coupled to the computer chip; and an antenna configured to send data collected onto the computer chip to a remote server. In an approach, a processor stimulating a cell sample. A processor senses the presence of at least two types of biomolecules released by the cell sample. A processor records data collected by the at least two chemical sensors. A processor sends the recorded data to a remote server.

Abstract: An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: A method of forming a vertical transport fin field effect transistor device is provided. The method includes replacing a portion of a sacrificial exclusion layer between one or more vertical fins and a substrate with a temporary inner spacer. The method further includes removing a portion of a fin layer and the sacrificial exclusion layer between the one or more vertical fins and the substrate, and forming a bottom source/drain on the temporary inner spacer and between the one or more vertical fins and the substrate. The method further includes replacing a portion of the bottom source/drain with a temporary gap filler, and replacing the temporary gap filler and temporary inner spacer with a wrap-around source/drain contact having an L-shaped cross-section.

Abstract: A memory device that includes an magnetoresistive random-access memory (MRAM) stack positioned on an electrode, a metal line in contact with the electrode, and a sidewall spacer abutting the MRAM stack. The memory device also includes a stepped reach through conductor having a first height portion of the stepped reach through conductor in an undercut region positioned between the sidewall spacer and the metal line, and a second height portion having a greater height dimensions than the first height portion abutting an outer sidewall of the sidewall spacer.

Abstract: An embedded eMRAM device for eFlash replacement including an MTJ pillar located between a top electrode and a bottom electrode for forming an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillar and surrounded by a second dielectric spacer. A bottom metal plate is disposed on opposing sides of the bottom electrode between first and second dielectric layers and is electrically separated from the bottom electrode by the first dielectric spacer. A top metal plate is disposed on opposing sides of the top electrode between third and fourth dielectric layers and is electrically separated from the top electrode by the second dielectric spacer. A bias voltage applied to the top metal plate and the bottom metal plate generates an external electric field on the MTJ pillar for creating a VCMA effect.

Abstract: A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming an MTJ stack including a reference layer, a tunnel barrier layer formed on the reference layer, a free layer formed on the barrier layer, and a cap layer formed on the free layer. The method also includes performing ion beam etching (IBE) through each layer of the MTJ stack to form at least one MTJ pillar. The method also includes forming an isolation layer on sidewalls of at least the tunnel barrier layer, the isolation layer comprising a same material as that of the tunnel barrier layer. A combined width of the isolation layer and the tunnel barrier layer is equal to or greater than a width of at least one of the reference layer and the free layer.

Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

Abstract: An access system having a communication component that interfaces with a first device and a second device, where the first device is located inside or on an entity and coupled to a biological organism of the entity, and where the second device is located outside the entity and a controller component that controls a function of the first device, employing the communication component, to provide treatment to the biological organism of the entity coupled to the first device based on a request received from the second device.

Abstract: A magnetic tunnel junction (MTJ) containing device is provided that includes an undercut conductive pedestal structure having a concave sidewall positioned between a bottom electrode and a MTJ pillar. The geometric nature of such a conductive pedestal structure makes the pedestal structure unlikely to be resputtered and deposited on a sidewall of the MTJ pillar, especially the sidewall of the tunnel barrier of the MTJ pillar. Thus, electrical shorts caused by depositing resputtered conductive metal particles on the sidewall of the tunnel barrier of the MTJ pillar are substantially reduced.

Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.

Abstract: Embodiments are directed to a method of forming a magnetic stack arrangement of a laminated magnetic inductor having a high frequency peak quality factor (Q). A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers in a first inner region of a laminated magnetic inductor. A second magnetic stack is formed opposite a surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The insulating layers are formed such that a thickness of an insulating layer in the second magnetic stack is greater than a thickness of an insulating layer in the first magnetic stack.

Abstract: Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

Abstract: An electrochemical sensor array includes a thermal oxide configured to interface with one or more analytes. There is a transistor device layer that includes a plurality of field effect transistors (FETs) on top of the thermal oxide. A contact and wiring structure layer is on top of the transistor device layer and operative to couple to control nodes of each of the plurality of FETs. The contact and wiring structure are on a side opposite to that of the thermal oxide.

Abstract: A magnetic random access memory (MRAM) array includes a plurality of MRAM cells, each of the MRAM cells including a magnetic tunnel junction (MTJ) stack disposed on a bottom metal via connecting the MTJ stack to a bottom conductive contact in a substrate, a plurality of top conductive contacts, each of the top conductive contacts disposed on a respective one of the MTJ stacks, and a plurality of unitary structures configured as a heat sink/magnetic shield disposed on a vertical portions of each of the MRAM cells, including vertical portions of the bottom metal vias, and under a portion of each of the MTJ stacks.

Abstract: A method of fabricating an MRAM device, the method including forming a magnetoresistive random-access memory (MRAM) stack comprising a first hard mask, forming sidewall spacers adjacent to the MRAM stack, forming a layer of interconnect metal around and above the MRAM stack, recessing the interconnect metal, forming a layer of a second hard mask over the interconnect metal, and patterning and etching the second hard mask and interconnect metal, forming interconnect metal lines.