Patents by Inventor Bruce B. Doris

Bruce B. Doris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210210413
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 8, 2021
    Inventors: Jingyun Zhang, Ruilong Xie, Alexander Reznicek, Bruce B. Doris
  • Patent number: 11056643
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. In the method there is provided an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a metal hardmask layer on a surface of said MTJ cap layer, the etch stop layer being subject to lithographic patterning and etching to form a patterned hardmask pillar structure. An encapsulating is performed to encapsulate, using an insulating material film, a top surface and sidewall surfaces of said patterned hardmask layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned hardmask without impacting MTJ stack performance.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nathan P. Marchack, Bruce B. Doris
  • Publication number: 20210194427
    Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11038097
    Abstract: Magnetic structures including magnetic inductors and magnetic tunnel junction (MTJ)-containing structures that have tapered sidewalls are formed without using an ion beam etch (IBE). The magnetic structures are formed by providing a material stack of a dielectric capping layer and a sacrificial dielectric material layer above a lower interconnect level. First and second etching steps are performed to pattern the sacrificial dielectric material layer and the dielectric capping layer such that a patterned dielectric capping layer is provided with a tapered sidewall. After removing the sacrificial dielectric material layer, a magnetic material-containing stack is formed within the opening in the patterned dielectric capping layer and atop the patterned dielectric capping layer. A planarization process is then employed to pattern the magnetic-containing stack by removing the magnetic material-containing stack that is located atop the patterned dielectric capping layer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Publication number: 20210175407
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11025234
    Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11024354
    Abstract: Circuits and methods are disclosed that, in embodiments, may be used for low power memory signal readout. In an embodiment, the circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11014127
    Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 25, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Publication number: 20210151503
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Application
    Filed: December 29, 2020
    Publication date: May 20, 2021
    Inventors: Pouya Hashemi, Bruce B.` Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Publication number: 20210151848
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11004933
    Abstract: Field effect transistors include a stack of nanowires of vertically arranged channel layers. A source and drain region is disposed at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Internal spacers are each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 11, 2021
    Assignee: Tessera, Inc.
    Inventors: Josephine B. Chang, Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 11004678
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Patent number: 10998854
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Publication number: 20210119113
    Abstract: A magnetic tunnel junction (MTJ) containing device is provided that includes an undercut conductive pedestal structure having a concave sidewall positioned between a bottom electrode and a MTJ pillar. The geometric nature of such a conductive pedestal structure makes the pedestal structure unlikely to be resputtered and deposited on a sidewall of the MTJ pillar, especially the sidewall of the tunnel barrier of the MTJ pillar. Thus, electrical shorts caused by depositing resputtered conductive metal particles on the sidewall of the tunnel barrier of the MTJ pillar are substantially reduced.
    Type: Application
    Filed: December 28, 2020
    Publication date: April 22, 2021
    Inventors: Nathan P. Marchack, Bruce B. Doris
  • Publication number: 20210119121
    Abstract: A bottom electrode structure for a magnetic tunnel junction (MTJ) containing device is provided. The bottom electrode structure includes a mesa portion that is laterally surrounded by a recessed region. The recessed region of the bottom electrode structure is laterally adjacent to a dielectric material, and a MTJ pillar is located on the mesa portion of the bottom electrode structure. Such a configuration shields the recessed region from impinging ions thus preventing deposition of resputtered conductive metal particles from the bottom electrode onto the MTJ pillar.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Nathan P. Marchack, Bruce B. Doris, Pouya Hashemi
  • Publication number: 20210091300
    Abstract: Magnetic structures including magnetic inductors and magnetic tunnel junction (MTJ)-containing structures that have tapered sidewalls are formed without using an ion beam etch (IBE). The magnetic structures are formed by providing a material stack of a dielectric capping layer and a sacrificial dielectric material layer above a lower interconnect level. First and second etching steps are performed to pattern the sacrificial dielectric material layer and the dielectric capping layer such that a patterned dielectric capping layer is provided with a tapered sidewall. After removing the sacrificial dielectric material layer, a magnetic material-containing stack is formed within the opening in the patterned dielectric capping layer and atop the patterned dielectric capping layer. A planarization process is then employed to pattern the magnetic-containing stack by removing the magnetic material-containing stack that is located atop the patterned dielectric capping layer.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 25, 2021
    Inventors: Bruce B. Doris, Oscar van der Straten, Alexander Reznicek, Praneet Adusumilli
  • Patent number: 10954544
    Abstract: Embodiments of the present invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a semiconductor substrate. The semiconductor device also includes a plurality of metal nanopillars formed on the substrate. The semiconductor device also includes an amperometric sensor associated with one of the plurality of nanopillars, wherein the amperometric sensor is selective to an enzyme-active neurotransmitter. The semiconductor device also includes a resistivity sensor associated with a pair of nanopillars, wherein the resistivity sensor is selective to an analyte.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Steven J. Holmes, Qinghuang Lin, Roy R. Yu
  • Patent number: 10957738
    Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bruce B. Doris, Chandrasekharan Kothandaraman, Nathan P. Marchack
  • Patent number: 10943732
    Abstract: A magnetic material stack comprises a first dielectric layer, a first magnetic material layer on the first dielectric layer, at least a second dielectric layer on the first magnetic material layer and at least a second magnetic material layer on the second dielectric layer. One or more surfaces of the layers are smoothed to remove at least a portion of surface roughness on the respective layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Patent number: 10944044
    Abstract: A memory structure is provided that avoids high resistance due to the galvanic effect. The high resistance is reduced and/or eliminated by providing a T-shaped bottom electrode structure of uniform construction (i.e., a single piece). The T-shaped bottom electrode structure includes a narrow base portion and a wider shelf portion. The shelf portion of the T-shaped bottom electrode structure has a planar topmost surface in which a MTJ pillar forms an interface with.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bruce B. Doris, Eugene J. O'Sullivan, Michael F. Lofaro