Abstract: A frequency control circuit for a single sideband receiver is disclosed wherein the local oscillator is swept at a first rate to enable the acquisition of a transmitted signal. When the signal is acquired, the local oscillator is swept at a second rate in an indicated direction in order to center the signal. Upon centering, the local oscillator is maintained at a frequency which centers the signal in response to the activation of a squelch detector.

Abstract: Disclosed, herein, is an Automatic Gain Control (AGC) signal processor and a method for generating an AGC signal in a phase-locked receiver. An incoming signal, exhibiting both coherent and incoherent characteristics, is filtered to obtain the desired bandwidth. The filtered signals are amplified to maintain an amplitude relationship between the coherent and incoherent signals. The incoherent signals are conditioned in the same circuit, but in a different manner, than coherent signals are conditioned. The conditioned signals are utilized to generate an AGC signal such that an AGC signal is generated in a single circuit for both coherent and incoherent signals, although by differing circuit responses, depending upon the conditioning of the incoming signal.The preferred embodiment of the novel AGC processing contemplates a full wave rectifier as its signal conditioner. Another embodiment contemplates negative peak detection as its conditioner.

Abstract: An automatic frequency control circuit for a single side band receiver employing a split-loop phase locked loop system is disclosed. Initially, both a first and second voltage controlled oscillator lock to a received pilot taken after the IF strip of the SSB receiver. Once lock is achieved, a sample is taken of the control line voltage of the first VCO whereafter the first VCO control line is held at the sampled voltage and will no longer track the received pilot until such time as the second VCO deviates from a predetermined range. Simultaneous to switching the first VCO, the loop filter of the second VCO is adapted to maintain identical loop dynamics both before and after switching control of the first VCO.

Abstract: A single sideband communications system conveying a message through a transmitter to one or more predetermined receivers which are enabled by a coded squelch signal unique to the predetermined receivers is disclosed. The transmitter comprises means to angle modulate both the pilot signal and the information bearing single sideband signal with the coded signal at a predetermined deviation and to transmit the resulting signal.Each receiver frequency control means tracks the frequency excursions of a selected portion of the transmitted signal up to predetermined limits so that the message can be demodulated without frequency distortion being introduced. Each receiver demodulates the coded squelch without interfering with the message demodulation or tracking functions and activates the receiver squelch of those preselected receivers.

Abstract: Hands-free control circuitry for a mobile radiotelephone is described that allows hands-free voice communications in a vehicular environment having a high level of ambient background noise. The hands-free control circuitry includes switches in the audio path from a microphone to the radio transmitter and the audio path from the radio receiver to a speaker, where, at all times, one audio path is closed to pass audio signal and the other audio path is open to block audio signals. The presence or absence of audio signals from the mobile party via the microphone and land party via the radio receiver is determined by separate detecting circuitry including a logarithmic amplifier, envelope detector, valley detector and summing circuitry, and comparator. Whenever the envelope of the audio signals exceeds its minima by an amount greater than a reference voltage, the detecting circuitry generates an output signal indicating that audio signals have been detected.

Abstract: An improved synchronizer for recovering the clock signal in split phase encoded data. The synchronizer includes a phase locked loop (PLL) which locks in phase with the encoded data at twice the data clock frequency. The output from the PLL is divided by two in a flip flop which is triggerable to produce an output at either 0.degree. or 180.degree. relative phase. The encoded data is detected in synchronism with the output of the flip flop and the resultant is integrated over each cycle of the flip flop signal. Comparator circuitry produces an error signal if the integrated value is within predetermined limits. A counter receives the error signals and, in response to a significant number thereof, activates the flip flop to produce its alternate phase output. In this manner, the flip flop output recovers the clock signal in proper phase.The synchronizer may be used in combination with additionally disclosed circuitry for use as a full demodulator.