Abstract: A voltage level sense circuit that has temperature compensation is disclosed. The circuit includes charge-sharing capacitors in each of an input leg and a reference leg. The charge-sharing capacitors are precharged to voltages that are integral multiples of the forward bias voltage drop across the base-emitter junction of a bipolar transistor. The bipolar transistors in the input leg differ from those in the reference leg, so that the difference in base-emitter on voltages increases with temperature. The increasing difference in base-emitter on voltage compensates for the decrease in the absolute value of the base-emitter on voltage with temperature. Voltage level sensing is accomplished by sampling the input voltage with a capacitor, charge-sharing the sampled voltage with one of the precharged charge-sharing capacitors, and coupling the charge-shared result to an input of a differential amplifier comparator.

Abstract: An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

Abstract: A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.

Abstract: A latch is provided in association with each non-volatile memory element used to store configuration information on a programmable logic device. In normal use, configuration information is written to the non-volatile memory elements in the usual manner. However, during testing volatile memory elements in the usual manner. However, during testing configuration information is written only to the latches associated with the non-volatile elements. The latches place the data stored therein onto the same architecture bit line used by the non-volatile memory elements, allowing chip configuration testing to be performed without actually writing to the non-volatile memory elements. The latches can be written to at a much faster speed than the non-volatile memory elements can be programmed, greatly decreasing the time needed for full testing of the programmable logic device.