Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. The signal comparison system includes a plurality of latches that receive a first signal and a second signal and that transmit a respective value of the first signal in response to a transition of the second signal. Delay mechanisms delay the transition of the second signal before the transition is received by latches so that the transition is delayed different amounts relative to each of the latches. A feedback mechanism receives the values transmitted by the latches and determines whether these values are logically equivalent. The feedback mechanism then transmits a feedback signal in response to a determination that one of the values is logically different than another of the values.

Abstract: A synchronization system synchronizes a first signal with a second signal. Data values of the first signal are stored in a first-in, first-out (FIFO) device in response to strobe signals that latch the first signal. The output of the FIFO device is clocked by clocks of the second signal. Therefore, the signal output by the FIFO device is synchronized with respect to the second signal. If the frequencies of the first signal and the second signal differ, then multiple FIFO devices are used to successively store the data of the first signal. In this regard, the signal output by the plurality FIFO devices has the same frequency as the second signal and has a bit length larger than the first signal.

Abstract: A signal comparison system determines whether a data signal is transitioning close to transitions of its clock signal, thereby causing possible errors in the sampling of the data signal. A first latch latches a data value of the data signal based on the transition of the clock signal. A delay mechanism delays the clock signal so that a second latch receives a delayed transition of the clock signal. The amount of delay corresponds to an amount of time to allow at least the data value latched into the first latch to stabilize. The second latch latches a data value of the data signal based on the delayed transition of the clock signal. A comparison mechanism compares the values of the two latches and outputs a particular logical value when the two values differ. The particular logical value indicates that the data signal transitioned so close to the clock signal that the data value of the first latch may be unreliable.

Abstract: A magnet set forth used is in a drain plug. A drain plug is assembled with an attached holder securing an inserted cylindrical magnet. The drain plug is formed of non ferrous material such as brass, aluminum, stainless steel, etc. It is constructed in accordance with industry standards to fit as a replacement device in oil drain pans, and is non ferrous material. It incorporates an extending threaded shaft. The holder is constructed with an axial passage there through having threads at the small end for threading through the drain plug. The passage extends fully through the device, interrupted by a transverse internal registration shoulder at the middle, and defines an extending skirt fitting loosely around an elongate cylindrical rare earth magnet.

Abstract: An automatic balancing circuit for a radio frequency mixer which reduces LO-IF signal leakage, as well as minimizing second order harmonic distortion products is described. The circuit couples to in-phase and out-of-phase signal lines originating from the mixer, and comprises a differential gain network, a differential phase shift network and a combiner. The networks operate under the control of a microprocessor, which adjusts the networks so that the LO leakage signals, when combined, are almost completely eliminated.

Abstract: A dumbbell shaped resonator efficiently couples IF signals from short transmission lines to an output transmission line at a radio frequency (RF) mixer's IF output port. The RF mixer uses short transmission lines and terminating resistors to match impedances within the mixer and to minimize the mixer's distortion. The RF mixer, including the dumbbell resonator, is constructed on a printed circuit board and has a low manufacturing cost. Alternatively, the output transmission line is center-tapped to provide a pair of IF signals having opposite phases.

Abstract: A wideband bandpass filter has a tank circuit connected between an input and output tapping circuit. The tank circuit contains a variable capacitor and an inductor in parallel. The tank circuit determines a center frequency for the bandpass filter. The input tapping circuit has an input variable impedance, and the output tapping circuit has an output variable impedance. The input and output variable impedances determine the continuously variable bandwidth of the filter.

Abstract: Disclosed is a software development tool for testing software on embedded microprocessor-based systems. A microprocessor emulator is used to provide the embedded system with access to external mass storage and other systems. The software development tool includes a software branch analyzer which is used to report whether branches in software under test were executed.