Abstract: An embodiment of the present invention is a technique for recording relevant information in a graphical user interface (GUI) window. Relevant information on an analysis window is saved in a summary report array using one of an automatic recording mode and a selective recording mode. The analysis window is part of the GUI to analyze state information from a panel dump file retrieved from a computer system. The saved relevant information is displayed on a report window.

Abstract: An embodiment of the present invention is a technique to provide a graphical user interface (GUI) to analyze memory operations in a computer system. A job summary window shows state information of jobs in at least a unit panel. The unit panel represents at least a functional unit in the computer system. A memory job window shows state information of memory jobs in a functional unit selected from the unit panel to provide diagnostic information to the user. The state information being obtained from a panel dump file retrieved from the computer system.

Abstract: An embodiment of the present invention is a technique for providing a graphical user interface (GUI) to view system state of a computer system. An error window displays an error condition of a failed unit in a plurality of functional units in a computer system based on a panel dump file. A warning window shows a warning condition that potentially causes a problem in analyzing system state of the computer system or the error condition.

Abstract: A digital data transport system where a serial stream of digital input data, received from a remote transmitter at an original clock frequency Fo, enters a FIFO repository at a variable frequency bit rate having an average frequency rate of If. A difference generator G, operating at the If frequency rate, receives a first feedback frequency clock signal Fr from a voltage controlled oscillator and a second feedback signal designating the current loading of the FIFO to provide a variable pulse stream to a driver whose output voltage controls the voltage controlled oscillator output frequency Fr so that it will match the average input frequency bit rate If (less the header bytes) in order to approximate the original clock frequency Fo.

Abstract: A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations.

Abstract: A method for using linear functions with counter modules for efficient implementation in PALs (Programmable Array Logic), or FPGAs (Field Programmable Gate Arrays) which generate digital control signals to a targeted digital device.An input setting pulsed digital signal A is upcounted and then is reduced by a downcounted feedback pulsed digital signal to produce a difference digital signal which involves adding an intercept value. The difference signal is multiplied by a slope-sensitivity parameter, each time expanding the numeric range and scope of the output digital control signal to the target digital device.

Abstract: A small first level cache and large second level cache support a central processor in accessing necessary data for processing. The second level cache holds tag address words each having two status bits V and R. The V bit indicates validity/invalidity status while the R bit informs the second level cache of the validity/invalidity status of the corresponding address in the first level cache. As a result of the status information between the two caches, the spy-snoop operation and invalidation operation cycles are minimized as to the use required of the processor bus, enabling higher efficiency processor operations. Utilization is made of a smart-fill algorithm which selects the address locations for placement of new data in a second level cache for a Write operation and after a Read-Miss by analyzing the status values (V,R) for each address in order to minimize the overwriting of valid cache data.

Abstract: A system and method for developing a digital control signal Y for setting a target module (D) according to a digital setpoint signal A, a digital feedback signal C, a difference digital signal X=A-C in an exponential relationship, such that Y=2.sup.X+1 -1. An N bit digital signal X is translated exponentially via a simple, non-complex programmable array logic unit to an expanded N+q digital bit signal providing an exponentially expanded response for the control signal Y to reset the target module D to an optimally desired setting.

Abstract: A system and method in a digital network for developing a digital output control signal Y which is of greater range and sensitivity than an input digital difference signal X wherein Y has a linear functional relationship to X according to a slope parameter "b". A method is developed for implementing the network with Field Programmable Gate Arrays (FPGAs) to develop the output control signal Y equal to a+bX on an expanded digital bus, where "a" is the intercept value of Y when X=0.

Abstract: A computer network serviced by a maintenance subsystem holds a control processing module (CPM) holding a Data Path Array as interface to a main memory module and I/O Module. A maintenance controller in the CPM has a preloaded Flash Memory unit holding all the necessary operating addresses and data which can be rapidly transferred via a special wide parallel high speed data bus to a data path array unit for subsequent conveyance to a channel microcode block in a main memory module. The operating data include channel microcode data necessary for the I/O Module to communicate with different types of peripheral devices.

Abstract: A central processing module (CPM) uses a data path array interface connecting dual system busses to a main memory module and I/O module. A maintenance controller in the CPM manages a programmable array logic unit controller to read out microcode words in the main memory module to verify their accuracy by comparison with an original data base of microcode words in a flash memory which was earlier pre-loaded from a maintenance subsystem. A high speed auxiliary data bus controlled by the programmable array logic controller, provides a high speed transfer channel for moving the main memory words to the maintenance controller which can then institute a verification procedure for each memory word.

Abstract: A multi-set cache structure, providing a first-level cache and second level cache to a processor, stores data words where each word holds two bytes and two status bits. Each cache set includes a Tag RAM for holding the address data words and a Parity RAM holding a parity bit for each byte and a parity bit for the two status bits. A programmable array logic control unit has a predictive generator logic unit to generate the proper "status parity bit" for each set of status bits (V,R) without need for waiting to calculate the status parity bit from the existing values of the two status bits.

Abstract: A computer network having a Control Processing Module (CPM) maintained by an external Maintenance Subsystem where the CPM has JTAG compatible digital units, but where the Cache Module is not JTAG compatible. Specialized transceivers having Boundary Scan Registers are activated to enable loading of address words in a Tag RAM while concomitantly placing correct initial parity data in a Parity RAM without need to continue communication with the external Maintenance Subsystem. The Boundary Scan Registers in said transceivers are set up to perform as up-counters to sequence through all address locations in the Tag RAM while a Control PAL calculates and places the associated parity values in each corresponding address location in the Parity RAM.

Abstract: A system and method for setting the sequence of processor operations in real time depending on the nature of Write commands and Send Message Commands in waiting queues which are ordinarily sequenced with Read OPs according to the sequential order that the commands are received. The system will give bus access to Read commands ahead of the Write commands and other commands in the waiting queues as long as data coherency will not be affected. Thus, the sequence of bus access can be modified to a different sequence giving priority-of-access to Read commands.

Abstract: A network in which an incoming word of 4 bytes and 4 parity bits is split into an address pointer and Tag address data into a Tag RAM storing two bytes which do not align with the incoming bytes and which leave a 2-bit (x,y,) crossed field. A programmable array logic Control PAL places correct parity values into a Parity RAM for the 2 stored bytes and later recreates the original word of 4 bytes and parity bits by using a flip-bit value (SPX) which simplifies the regeneration of correct parity values.

Abstract: A network comprising a central processing module and maintenance subsystem which provides a system for rapid loading of instruction words in a microcode RAM whereby microcode instruction words from the maintenance subsystem are preliminarily loaded into a flash memory in the central processing module. A maintenance controller transfers the microcode instruction words from the flash memory over a transfer bus to a data path array which connects to a processor-instruction memory bus for enabling microcode addresses and data words to be rapidly transferred into a microcode RAM instruction memory. A programmable controller activated by the maintenance controller in the central processing module then regulates the transfer of data to the microcode RAM by providing incrementation of the addresses of the instruction words on an automatic basis and thus relieving the processor of this function.

Abstract: An optimization system for the cache-fill operation in a multi-set cache memory operates to select that cache-set which indicates it has invalid data therein and/or also indicates that an associated upper level cache has correspondingly invalid data. When no data invalidity is indicated, then a random counter is used to arbitrarily select an address for one set of the multiple-set cache units for the data-fill operation.

Abstract: An initiator-sending module requests bus access on a retry-basis after a "bus-error" or "receiver-not ready" situation. The bus request retry is provided with an adjustable wait delay period tailored to the specific system and provides a programmable random wait delay which also includes a minimum time delay period programmed for that specific system network.

Abstract: A computer network is connected via dual system busses to multiple digital modules such as a Central Processing Module with a Central Processor and also to a main memory module, plus an I/O module in addition to other possible modules, such as other Central Processing Modules. The Central Processor has a cache memory which is accessed on the basis of adjustable priorities, the most normal situation being that the Central Processor has first priority to cache access. However, under certain other conditions, the priority of access to cache is adjusted to give priority to an invalidation queue when it is almost full of invalidation addresses to be processed on invalidation cycles to the cache memory. Another priority is given to the invalidation queue after a Read-Lock operator is initiated by the processor. The resulting adjustable priorities work to optimize the integrity and speed of throughput of the system.

Abstract: A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.