Abstract: A system whereby a microcode RAM in a central processing module can have each microcode word rapidly accessed and transferred to a maintenance controller to compare each accessed microcode word with a corresponding microcode word in a set of microcode words which were pre-loaded in a flash memory.

Abstract: A central processor is serviced by a multi-way cache module having N cache sets some of which can be taken off-line by a maintenance subsystem. Masking logic is provided to control the fill-operation cycles to cache so that equitable distribution of fill-data is allocated among only those cache sets remaining on-line.

Abstract: A system for interleaving invalidation cycles to a cache memory during those periods when the processor is waiting or has not need to access cache memory. These periods occur during a Read-Miss operation or when bus access delays to main memory cause the processor to wait for receipt of data, or when the processor communicates with network modules other than the cache memory and main memory.

Abstract: A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority operation which will give priority to invalidation cycles in the cache over the priority of the processor's cache access. When the FIFO queue indicates that it is almost empty, then the priority of the cache access by the processor is re-established as it was in normal conditions. The system operates concurrently in a self-regulating manner to load and unload addresses into the FIFO queue while also giving priority to flushing out the queue with invalidation cycles when preset upper limits are reached.

Abstract: A multi-set cache module is initiated by a maintenance subsystem to function with all sets on-line or only some sets on-line. A parity error sensing switch flip-flop unit will selectively disable only those sets which indicate parity error problems except when multiple simultaneous "hit" signals occur, in which case, the switch unit disables all of the cache sets.

Abstract: An enhanced computer system architecture provides a processor supported by a general cache and a mini-cache wherein the mini-cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to access main memory. The mini-cache stores frequently used data words and is refilled concurrently during processor command execution and is settable for handling data words or code words or both. A data queue storage stores a block of words which duplicate words in main memory. If the requested address matches an address register block in the mini-cache, the data queue store will make the words in the data queue available to requests from the processor. The mini-cache also monitors the system bus for any "write" operations which might change the validity of the data in the address register block of the mini-cache. In this case, the data stored in the mini-cache is invalidated and cannot be used by the processor.