Abstract: A transfer apparatus for moving an item from a first to a second location. The apparatus includes a base, a platform movably supported by the base, a bracket movably supported by the platform, a table, and at least one transfer unit movably connected to the platform and perpendicularly displaceable with respect thereto. The platform and bracket are each provided with a follower that is operatively connected to a cam, and both of the cams are connected to a single rotatable shaft. In operation the shaft, which is connected to a suitable motive source, rotates the cams, which reciprocally move the platform and bracket in a generally parallel directions. As the platform is moved by its cam, the transfer unit is displaced parallel to the base. As the bracket is moved by its cam, the bracket displaces the table perpendicularly to the base, which, in turn displaces the transfer unit perpendicularly to the platform.

Abstract: Battery assemblies are disclosed which may include a plurality of battery cells positioned in trays which are stacked. The battery cells of each tray may be electrically connected together. The battery trays may include a battery support which extends under and supports a middle portion of the battery cells of the respective battery tray. The battery support may be a thermal sink for the battery cells.

Abstract: Battery terminal systems are provided for coupling a first battery to a second battery. The battery terminal systems may include bases assembled to the terminals of the first battery and the second battery. The bases being coupled to a jumper to electrically couple the first battery to the second battery.

Abstract: A method is disclosed. The method includes identifying locations of one or more points of interest, identifying an area of interest on a map displayed on a display device, identifying points of interest within the area of interest, selecting a level of detail and clustering the points of interest within the level of detail based on the location of the points of interest relative proximity to other points of interest.

Abstract: A data processing system includes a plurality of transaction masters (4, 6, 8, 10) each with an associated local cache memory (12, 14, 16, 18) and coupled to coherent interconnect circuitry (20). Monitoring circuitry (24) within the coherent interconnect circuitry (20) maintains a state variable (flag) in respect of each of the transaction masters to monitor whether an exclusive store access state is pending for that transaction master. When a transaction master is to execute a store-exclusive instruction, then a current value of the subject state variable for that transaction master is compared with a previous value of that variable stored when the exclusive store access was setup. If there is a match, then store-exclusive instruction is allowed to proceed and the state variables of all other transaction masters for which there is a pending exclusive store access state are changed. If there is not a match, then the execution of the store-exclusive instruction is marked as failing.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: Interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device. The circuitry including: at least one input for receiving transaction requests from at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; and at least one path for transmitting transaction requests between at least one input and at least one output. Also includes is control circuitry for routing the received transaction requests from at least one input to at least one output and responds to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths. Barrier transaction requests include an indicator of transaction requests whose ordering is to be maintained.

Abstract: Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.

Abstract: A data processing assembly includes one or more hosts connected to one or more I/O Expansion Drawers. Assignment state information is stored on the Expansion Drawer to convey the assignment state of Expansion Drawer(s) resources to the hosts. The host retrieves the assignment state and, from it, determines, for each Expansion Buss cable connected to the host, the number of Expansion Cards in the Expansion Drawer to configure. A change in the number of Expansion Cards in the expansion apparatus may necessitate a change in the assignment state, which can be electronically accommodated (as opposed to a manual reconfiguration). Similarly, a failure of an Expansion Buss cable is addressed by electronically reassigning resources to another host or to the same host over a different Expansion Buss cable without the need for further manual intervention. The assembly is capable of verifying correct cable connection between a host and the Expansion Drawer.

Abstract: The initiator device receives requests from and issues transaction requests to a recipient device via an interconnect. A barrier generator generates barrier transaction requests indicating to the interconnect that an ordering of some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request. In response to a synchronize request querying progress of a subset of transaction requests, the initiator device actions any pending transaction requests within the subset of transaction request and the barrier generator generates and issues a barrier transaction request to the interconnect. In response to receiving a response to the barrier transaction request, the initiator device issues an acknowledge signal as a response to the synchronize request.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: Initiator devices for generating transaction requests and recipient devices for receiving them are disclosed. The recipient devices accept transaction requests where there is available buffer storage for the transaction request. If there is no storage space available an acknowledgement signal generator generates and outputs a reject acknowledgement signal indicating a request has been received but has not been accepted by the recipient device. A credit generator can reserve at least one available storage location in the buffer and generate a credit grant for an initiator device that sent one of the transaction requests that was not accepted by the recipient device. The credit grant indicates to the initiator device that there is at least one reserved storage location, such that a subsequent transaction request from the initiator device will be accepted by the recipient device.

Abstract: A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache.

Abstract: A method and system for collecting and transmitting data across or through a firewall using HTTP and/or XML between computer systems that do not otherwise grant access to each other. A method and system for preparing data reports using data and report generation modules using HTTP and/or XML between computer systems.

Abstract: In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Abstract: A battery assembly includes a first cell and a second cell adjacent the first cell. A first insulator and a second insulator extend over and encapsulate first electrode and second electrode. A shell extends over the first and second insulators thereby encapsulating the first and second insulators. A mechanical connection is defined between the first insulator of the first cell and the second insulator of the second cell.

Abstract: A latching device secures a strap to a piece of sports equipment. The latching device includes a buckle and a base. The buckle has a main body portion. The main body portion has an integrally formed collet and has a first slot and a second slot. The first and second slots each having a plurality of teeth shaped members that are configured to secure the strap to the buckle. The base is attached to the piece of sports equipment. The base has a first shaft and an annular ring. The first shaft has a first end and a second end. A ball shaped member is attached to the first end of the first shaft. The annular ring is formed on a periphery of the base surrounding the first shaft. The ball shaped member is releasably received in the collet to releasably engage the buckle with the base.

Abstract: A battery assembly includes a first cell and a second cell adjacent the first cell. A first insulator and a second insulator extend over and encapsulate first electrode and second electrode. A shell extends over the first and second insulators thereby encapsulating the first and second insulators. A mechanical connection is defined between the first insulator of the fist cell and the second insulator of the second cell.

Abstract: Interconnect logic is provided for coupling master logic units and slave logic units within a data processing apparatus to enable transactions to be performed. Each transaction comprises an address transfer from a master logic unit to a slave logic unit and one or more data transfers between that master logic unit and that slave logic unit. The interconnect logic comprises a plurality of connection paths for providing at least one address channel for carrying address transfers and at least one data channel for carrying data transfers, and control logic is used to control the use of the at least one address channel and the at least one data channel in order to enable the transactions to be performed.

Abstract: Interconnect circuitry configured to provide routes for interconnecting several initiator devices and at least one recipient device including a memory. At least one of the initiator devices has a cache for storing a local copy of a subset of data items stored in the memory. The interconnect circuitry includes: a plurality of input ports and at least one output port; a plurality of paths for transmitting the transaction requests between the inputs and the at least one output; coherency control circuitry for maintaining an order in which at least some of the transaction requests to a same data storage location proceed through the interconnect circuitry. The interconnect circuitry is configured not to control the writeback transaction requests with the coherency control circuitry, such that the writeback transaction requests proceed independently of transaction requests routed through the coherency control circuitry.