Abstract: A memory (400) includes a sense amplifier (500) formed with current-to-voltage converters (512, 513) connected to multiple bit lines, with a common current source (548) forming a current reference, and a common latching comparator (530). A column decode select circuit (515) which selects one of the multiple bit lines is interposed between the current-to-voltage converters (512, 513) and an input of the latching comparator (530). The distribution of the components of the sense amplifier (500) allows operation at low power supply voltages. The sense amplifier (500) uses a clamp and a loading device to establish a first discharge rate on a reference input of the latching comparator (530). The state of the selected memory cell establishes a second discharge rate on another input of the latching comparator (530), which is greater or less than the first discharge rate depending on the state of the memory cell. Portions of the comparator (530) also double as latches during a program mode.

Abstract: A control gate driver circuit (900) provides a variety of voltages to a control gate (21) of a floating gate nonvolatile memory cell (10) using a single circuit. During a read mode, a bias circuit (920) and a reference transistor (925) bias a pass transistor (936) connected to the output of a level shifter (910) to be slightly conductive and thus biases control gates without the need for a charge pump. During programming, a pulse circuit (940) gradually builds the program voltage provided to cells along a selected row, allowing the use of smaller pass transistors (932, 934) and smaller capacitors in the charge pump of the supply (930). Cells in an unselected row are driven to a different voltage, decreasing junction leakage and maintaining high disturb voltage in cells in the unselected row. The control gate driver circuit (900) is implemented using only P-channel pass transistors, eliminating the need for a costly triple-well process.

Abstract: A memory array (25) having a selected memory cell (10) and an unselected memory cell (30) is programmed and read. Each memory cell in the memory array (25) contains an isolation transistor (22) and a floating gate transistor (23). To program the selected memory cell (10), programming voltages are applied to a control gate line (21), a drain line (14), an isolation line (19), and a source line (12). To reduce the effects of the drain disturb problem, a gate terminal (32) of the unselected memory cell (30) is held at a positive voltage. To read selected memory cell (10), a read voltage is applied to an isolation gate line (31) of unselected memory cell (30) which insures that the unselected memory cell (30) does not conduct or contribute to leakage current and power consumption during the read operation.

Abstract: A process for fabricating an improved nonvolatile memory device includes the formation of a control gate electrode (70) which overlies a floating gate electrode (42) and is separated therefrom by an inter-level-dielectric layer (62). The control gate electrode (70) and the underlying floating gate electrode (42) form a stacked gate structure (72) located in the active region (44) of a semiconductor substrate (40). An electrically insulating sidewall spacer (54) is formed at the edges of the floating gate electrode (42) and electrically isolates the control gate (70) from the semiconductor substrate (40). During the fabrication process, implanted memory regions (56, 58) are formed in the active region (44) prior to the formation of control gate electrode (70). A word-line (68) and the control gate (70) are formed by anisotropic etching of a semiconductor layer (66), which is deposited to overlie inter-level-dielectric layer (62).

Abstract: A nonvolatile memory (20) includes an array of floating gate transistors (22) organized as rows and columns. Word lines of adjacent rows are coupled together to form shared word lines. In one embodiment, a coupling transistor (56-61) is used to couple the sources of the floating gate transistors (36, 39-55) of a row to a predetermined potential in response to the shared word line being selected. The sources of the unselected floating gate transistors of the array (22) are isolated. In another embodiment, an inverter (113, 114, and 115) couples the sources to zero volts in response to the shared word line being selected. The conductivity of the floating gate transistors (36, 39-55) is controlled in response to the logic state of the shared word lines to ensure that unselected cells do not adversely affect the operation of the nonvolatile memory.

Abstract: A high voltage charge pump (65) for operation at low power supply voltages includes a plurality of series connected pump stages (66), a predriver logic circuit (68), and two pump driver circuits (70 and 72). The predriver logic circuit (68) receives an external clock signal and provides internal clock signals to the pump driver circuits (70 and 72). The pump driver circuits (70 and 72) provided boosted clock signals to the series connected pump stages (66). The boosted clock signals are provided at a voltage greater than a magnitude of a power supply voltage. By using a boosted clock signal, the charge pump (65) is capable of operating in applications with low power supply voltages, such as 3.3 volts.

Abstract: A charge pump with controlled ramp rate (200) includes a charge pump (65), an RC differentiator circuit (258), and a trigger circuit (238). The charge pump (65) receives a clock signal and provides a high output voltage for programming and erasing an EEPROM. The RC differentiator circuit (258) provides a control voltage that is proportional to the ramp-up rate of the high output voltage. The trigger circuit (238) receives the control voltage, and provides a control signal to disable the charge pump (65) if the ramp-up rate exceeds a predetermined rate. When the ramp-up rate falls below the predetermined rate, the trigger circuit (238) provides a control signal to enable the charge pump (65). The trigger circuit (238) has hysteresis to regulate its switching point. Controlling the ramp-up rate of the output voltage reduces the peak tunneling current in the EEPROM cell to increase reliability.

Abstract: A DRAM contains both driver control logic and level shifting driver circuitry to generate a voltage boosted word-line signal. The driver control logic receives timing signals and row address information to provide timing control signals for the level shifting driver. The level shifting driver provides a voltage boosted word-line signal for a predetermined period of time in response to the timing control signals. Furthermore, the driver control logic provides control to the level shifting driver circuit to assure that transistors that drive the word-line signal are not damaged by voltage during a switching transition.

Abstract: A DRAM has both a distributed row address decode and a distributed timing control to generate required timing signals. A level of decoding is implemented within each of local row decoders to generate critical timing signals for each of a plurality of DRAM bit cell arrays. Word line signals from an output of each of the local row decoders are interleaved. The interleaved word line signals permit a high density DRAM semiconductor manufacturing process to utilize a differing pitch for each of a plurality of levels of interconnect. A first level of interconnect has a pitch which is significantly smaller than the pitch of a second interconnect level positioned above the first level of interconnect.

Abstract: A non-volatile memory has memory cells which are programmable to a programmed state from an unprogrammed state. Programming changes the conductivity of the memory cell which is being programmed. The particular state of a selected memory cell is determined by comparing the conductivity of the selected memory cell to that of a normal reference. In order to assure that a memory cell has been programmed to a conductivity which is sufficient for reliable detection, a substitute reference with a different conductivity is used immediately after programming. If the selected cell is detected as being programmed when compared to the substitute reference, the selected cell is then determined to have been sufficiently programmed for reliable detection using the normal reference.

Abstract: A memory has an address buffer which receives a row address and a column address and outputs these buffered address signals to a predecoder. A row decoder and column decoder use predecoded signals provided by the predecoder to select a row and a column from a main array. A redundant row is provided to replace a defective row from the main array. A programmable redundant decoder is programmable to select the redundant row in response to the predecoder signals which select the defective row.

Abstract: A clock generator is used in a non-volatile memory to generate a timing signal for clocking a sense amplifier. The timing signal duration is timed using circuit features which also affect the rate with which data can be sensed by the sense amplifier. The clock generator includes a reference word line which is analogous to an accessed word line, a memory cell which establishes a reference current analogous to that provided by an accessed cell, and a current mirror which uses the reference current to charge a reference line analogous to a bit line. The duration of the timing signal is established by the reference line reaching a predetermined voltage.

Abstract: A non-volatile memory has memory cells which have a first or a second conductivity. A reference current is established through an unprogrammed reference cell which has the first conductivity. A logic state current is established through a selected memory cell. The magnitude of the logic state current is related to the conductivity of the selected memory cell. A current comparator is used to compare the reference current to the logic state current. If the logic state current is related to the first conductivity state, an output signal is provided at a first logic state. If the logic state current is related to the second conductivity state, the output signal is provided at a second logic state.

Abstract: Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a data line while the sense amplifier is amplifying the signal provided by the memory cell. The effect of coupling the bit line to the data line is to hinder the refresh of the selected memory cell because the bit line does not reach full power supply voltage due to the loading by the data line. Full refresh is obtained by keeping the word line enabled for a predetermined time following the bit line being decoupled from the data line so the sense amplifier can bring the bit line to full power supply potential.

Abstract: A substrate bias pump is provided with a signal controlled circuit for coupling a negatively charged pump node to a substrate with a negligible voltage loss therebetween. A transistor, connected as a capacitor, with a source and a drain connected together for receiving a pump signal, and a gate connected to the pump node, avoids adding parasitic capacitance to the pump node.