Patents by Inventor Bruce L. Worthington
Bruce L. Worthington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10102102Abstract: A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.Type: GrantFiled: December 18, 2015Date of Patent: October 16, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Bruce L. Worthington, Jason Carl Hendrickson, Robert P. Fitzgerald, Stuart Sechrest, Changjiu Xian, Qi Zhang
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Patent number: 9760300Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.Type: GrantFiled: November 30, 2015Date of Patent: September 12, 2017Assignee: Microsoft Technology Licensing, LLCInventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Swaroop Kavalanekar
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Publication number: 20160110279Abstract: A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.Type: ApplicationFiled: December 18, 2015Publication date: April 21, 2016Inventors: Bruce L. Worthington, Jason Carl Hendrickson, Robert P. Fitzgerald, Stuart Sechrest, Changjiu Xian, Qi Zhang
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Publication number: 20160077760Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.Type: ApplicationFiled: November 30, 2015Publication date: March 17, 2016Applicant: Microsoft Technology Licensing, LLCInventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Swaroop Kavalanekar
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Patent number: 9235500Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.Type: GrantFiled: December 7, 2010Date of Patent: January 12, 2016Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Swaroop Kavalanekar
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Patent number: 9223675Abstract: A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.Type: GrantFiled: November 17, 2011Date of Patent: December 29, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Bruce L. Worthington, Jason Carl Hendrickson, Robert P. Fitzgerald, Stuart Sechrest, Changjiu Xian, Qi Zhang
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Publication number: 20150253841Abstract: Techniques for storage device power management are described that enable coordinated buffer flushing and power management for storage devices. In various embodiments, a power manager can coordinate the flushing of pending or “dirty” data from multiple buffers of a computing device in order to reduce or eliminate interleaved (e.g., uncoordinated) data operations from the multiple buffers that can cause shortened disk idle periods. By so doing, the power manager can selectively manage power states for one or more power-managed storage devices to produce longer idle periods. For example, information regarding the status of multiple buffers can be used in conjunction with analysis of historical I/O patterns to determine appropriate times to spin down a disk or allow the disk to keep spinning. Additionally, user-presence information can be utilized to tune the aggressiveness of buffer coordination and state transitions for power-managed storage devices to improve performance.Type: ApplicationFiled: May 26, 2015Publication date: September 10, 2015Inventors: Changjiu Xian, Bruce L. Worthington
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Patent number: 9015441Abstract: A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.Type: GrantFiled: April 30, 2010Date of Patent: April 21, 2015Assignee: Microsoft Technology Licensing, LLCInventors: Bruce L. Worthington, Vishal Sharda, Qi Zhang, Mehmet Iyigun, Yevgeniy Bak
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Patent number: 8990538Abstract: A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.Type: GrantFiled: November 5, 2010Date of Patent: March 24, 2015Assignee: Microsoft CorporationInventors: Bruce L. Worthington, Swaroop V. Kavalanekar, Robert P. Fitzgerald, René A. Vega
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Patent number: 8812817Abstract: A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.Type: GrantFiled: June 28, 2013Date of Patent: August 19, 2014Assignee: Microsoft CorporationInventors: Jeffrey C. Fuller, Thomas J. Ootjers, Bruce L. Worthington
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Patent number: 8645592Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.Type: GrantFiled: October 30, 2012Date of Patent: February 4, 2014Assignee: Microsoft CorporationInventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
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Patent number: 8645734Abstract: A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement. The policies may allow some processes to operate while consuming less energy, while other processes may be configured to maximize performance.Type: GrantFiled: October 24, 2012Date of Patent: February 4, 2014Assignee: Microsoft CorporationInventors: Stephen R Berard, Sean N McGrane, Bruce L Worthington
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Publication number: 20130346692Abstract: A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.Type: ApplicationFiled: June 28, 2013Publication date: December 26, 2013Inventors: Jeffrey C. Fuller, Thomas J. Ootjers, Bruce L. Worthington
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Patent number: 8495299Abstract: A cache controller in a computer system is configured to manage a cache. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.Type: GrantFiled: November 16, 2009Date of Patent: July 23, 2013Assignee: Microsoft CorporationInventors: Jeffrey C. Fuller, Bruce L. Worthington, Thomas J. Ootjers
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Patent number: 8479214Abstract: Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.Type: GrantFiled: September 30, 2008Date of Patent: July 2, 2013Assignee: Microsoft CorporationInventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
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Publication number: 20130132616Abstract: A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.Type: ApplicationFiled: November 17, 2011Publication date: May 23, 2013Applicant: MICROSOFT CORPORATIONInventors: Bruce L. Worthington, Jason Carl Hendrickson, Robert P. Fitzgerald, Stuart Sechrest, Changjiu Xian, Qi Zhang
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Patent number: 8346995Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.Type: GrantFiled: September 30, 2008Date of Patent: January 1, 2013Assignee: Microsoft CorporationInventors: Dustin L. Green, Yau Ning Chin, Bruce L. Worthington
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Patent number: 8321703Abstract: A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement. The policies may allow some processes to operate while consuming less energy, while other processes may be configured to maximize performance.Type: GrantFiled: December 12, 2009Date of Patent: November 27, 2012Assignee: Microsoft CorporationInventors: Stephen R. Berard, Sean N. McGrane, Bruce L. Worthington
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Publication number: 20120284544Abstract: Techniques for storage device power management are described that enable coordinated buffer flushing and power management for storage devices. In various embodiments, a power manager can coordinate the flushing of pending or “dirty” data from multiple buffers of a computing device in order to reduce or eliminate interleaved (e.g., uncoordinated) data operations from the multiple buffers that can cause shortened disk idle periods. By so doing, the power manager can selectively manage power states for one or more power-managed storage devices to produce longer idle periods. For example, information regarding the status of multiple buffers can be used in conjunction with analysis of historical I/O patterns to determine appropriate times to spin down a disk or allow the disk to keep spinning. Additionally, user-presence information can be utilized to tune the aggressiveness of buffer coordination and state transitions for power-managed storage devices to improve performance.Type: ApplicationFiled: May 6, 2011Publication date: November 8, 2012Applicant: MICROSOFT CORPORATIONInventors: Changjiu Xian, Bruce L. Worthington
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Publication number: 20120284543Abstract: Techniques for user input triggered device power management are described that enable user inputs and activities to cause selective changes in power states for a device. Power can be boosted to a high power state to improve responsiveness for designated inputs and/or activities. When responsiveness is deemed less important in connection with particular inputs and/or activities, a low power state can be set to reduce energy consumption. In at least some embodiments, selectively switching between power states includes detecting various user inputs at a device and filtering the inputs to select power states associated with the user inputs. The device can then be operated in a selected power state until a transition to a different power state is triggered by occurrence of designated events, such as running of a set time interval, further user input, and/or completion of user activity.Type: ApplicationFiled: May 2, 2011Publication date: November 8, 2012Applicant: MICROSOFT CORPORATIONInventors: Changjiu Xian, Bruce L. Worthington