Abstract: Techniques for implementing processor state-based thread scheduling are described that improve processor performance or energy efficiency of a computing device. In one or more embodiments, a power configuration state of a processor is ascertained. The processor or another processor is selected to execute a thread based on the power configuration state of the processor. In other embodiments, power configuration states of processor cores are ascertained. Power configuration state criteria for the processor cores are defined based on the respective power configuration states. One of the processor cores is then selected based on the power configuration state criteria to execute a thread.

Abstract: Batching techniques are provided to maximize the throughput of a hardware device based on the saturation point of the hardware device. A balancer can determine the saturation point of the hardware device and determine the estimated time cost for IO jobs pending in the hardware device. A comparison can be made and if the estimated time cost total is lower than the saturation point one or more IO jobs can be sent to the hardware device.

Abstract: A computer system may manage objects in memory to consolidate less frequently accessed objects into memory regions that may be operated in a low power state where the access times may increase for the memory objects. By operating at least some of the memory regions in a low power state, significant power savings can be realized. The computer system may have several memory regions that may be independently controlled and may move memory objects to various memory regions in order to optimize power consumption. In some embodiments, an operation system level function may manage memory objects based on parameters gathered from usage history, memory topology and performance, and input from applications.

Abstract: Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Abstract: A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.

Abstract: A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.

Abstract: Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.

Abstract: A computer system may place memory objects in specific memory physical regions based on energy consumption and performance or other policies. The system may have multiple memory regions at least some of which may be powered down or placed in a low power state during system operation. The memory object may be characterized in terms of access frequency, movability, and desired performance and placed in an appropriate memory region. In some cases, the memory object may be placed in a temporary memory region and later moved to a final memory region for long term placement.

Abstract: A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

Abstract: A computer system may manage objects in memory to consolidate less frequently accessed objects into memory regions that may be operated in a low power state where the access times may increase for the memory objects. By operating at least some of the memory regions in a low power state, significant power savings can be realized. The computer system may have several memory regions that may be independently controlled and may move memory objects to various memory regions in order to optimize power consumption. In some embodiments, an operation system level function may manage memory objects based on parameters gathered from usage history, memory topology and performance, and input from applications.

Abstract: A component level power monitoring system may analyze workloads by determining energy consumed by individual components for the workload. By comparing different system configurations or by modifying the software operation, an optimized workload may be performed per energy consumed. In some embodiments, several system configurations may be attempted to determine an optimized system configuration. In other embodiments, a monitoring system may change how an application is executed by changing thread affinity or otherwise assigning certain operations to specific components. The component level monitoring may be implemented as operating system level function calls.

Abstract: An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.

Abstract: Batching techniques are provided to maximize the throughput of a hardware device based on the saturation point of the hardware device. A balancer can determine the saturation point of the hardware device and determine the estimated time cost for IO jobs pending in the hardware device. A comparison can be made and if the estimated time cost total is lower than the saturation point one or more IO jobs can be sent to the hardware device.

Abstract: Improved hardware throughput can be achieved when a hardware device is saturated with IO jobs. Throughput can be estimated based on the quantifiable characteristics of incoming IO jobs. When IO jobs are received a time cost for each job can be estimated and stored in memory. The estimates can be used to calculate the total time cost of in-flight IO jobs and a determination can be made as to whether the hardware device is saturated based on completion times for IO jobs. Over time the time cost estimates for IO jobs can be revised based on a comparison between the estimated time cost for an IO job and the actual time cost for the IO job using aggregate IO job completion sequences.

Abstract: Techniques are disclosed for managing the flow of IO jobs from a client to a hardware device such that resource starvation is reduced without significantly impacting throughput. Each flow can be assigned an amount of time that a hardware device can deplete completing IO jobs from the client. When the allocated amount of time is used IO jobs associated with the client can be stored in a queue until the client obtains more time.

Abstract: Processor interrupt determination procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable by a computer to determine, based on a performance goal, which of a plurality of processors is to be targeted by a device that is to perform an input/output operation when an interrupt message is discovered that is from the device and that targets the determined processor. The interrupt message is communicated to the device to indicate availability of the determined processor for use by the device. When an interrupt message is discovered that is from the device and that targets an alternative processor near the determined processor when compared with other processors in the plurality of processors, the interrupt message that targets the alternative processor is communicated to the device to indicate availability of the alternative processor for use by the device.

Abstract: Processor selection procedures are described. In an implementation, one or more computer-readable media comprise instructions that are executable to cause a processor executing the instructions to select, based on a performance goal, which of a plurality of processors is to further handle a device interrupt and when the selected processor is available, notify the selected processor to further handle the device interrupt.

Abstract: An interrupt redirection and coalescing system for a multi-processor computer. Devices interrupt a processor or group of processors using pre-defined message address and data payloads communicated with a memory write transaction over a PCI, PCI-X, or PCI Express bus. The efficiency of processing may be improved by combining multiple interrupt notifications into a single interrupt message to a processor. For some interrupts on a multi-processor computer, such as those signaling completion of an input/output (I/O) operation assigned to a device, the efficiency of processing the interrupt may vary from processor to processor. Processing efficiency and overall computer system operation may be improved by appropriately coalescing interrupt messages within and/or across a plurality of queues, where interrupts are queued on the basis of which processor they target.