Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Abstract: A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.

Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.

Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.

Abstract: Technologies for performing tensor operations in memory include a memory comprising media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is to access matrix data from the memory media, perform a tensor operation on the matrix data, and write, to the memory media, resultant data indicative of a result of the tensor operation.

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.

Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.

Abstract: Examples include techniques for self-healing of a processor in a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores detect an error causing a core failure, update processor configuration information that reflects the core failure, and cause reset and initialization of the processor using the updated processor configuration information.

Abstract: An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

Abstract: Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

Abstract: A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.